The application of 3D-LSIs for character recognition image sensing processors in described. Three-dimensional LSIs will achieve very high performance by exploiting the structural parallelism by way of the inherence parallelism of an algorithm. As the first step, the three-story structured image sensing processor was implemented integrating 210 pixel photodiodes and 10.4 thousand transistors on a 5.04 mm 11.20 mm die. It is able to sense 6 characters of image at the same time and recognize 64 kind of characters, those are alphabet in capital and lower case, Arabic numerals and some symbols, each consists of 5 7 bit matrix. A four-story structured image sensing processor, which is the second step for realizing the advanced image sensor, integrating 5040 pixel photodiodes and 0.22 million transistors on a 14.3 mm square single die is currently under implementation. The present chip allows 20 times larger degree of data parallelism and several 10 times higher speed of data matching than the previous chip. And some other advantages have been achieved in its functions. Before the implementation of the present chip, its test element circuits were fabricated successively and the functions of the circuit blocks were confirmed. Each floor of 0.6 µm thick SOI film was recrystallized with Ar laser irradiation by the M-shaped beam method with parallel groove structure. The grain boundaries and defects are confined within each ridge region and the defect free single crystal Si film, whose crystal orientation is aligned to the (100) silicon on the lower floor, is grown on each groove region. The maximum temperature of atmosphere during fabrication process was 900. Both chips are made of a number of simple processing elements working in parallel to speed up a computation. So far only several floors can be fabricated as a single die. However the technology has been steadily progressing. The real "intelligent" image sensing processor will be implemented in the near future with 3D integration technology.

A new multiple-valued mask-ROM cell and a technique suitable for data detection are proposed. The information is programmed in each of the memory cells as both the threshold voltage and the channel length of the memory cell transistor, and the stored data are detected by selecting the bias condition of both the word-line and the data-line. The datum stored in the channel length is read-out using punch-through effect at the high drain voltage. The feasibility of this mask-ROM's is studied with device simulation and circuit simulation. With this design, it would be possible to get the high-density mask-ROM's, which might be faster in access speed and easier in fabrication process than the conventional ones. Therefore, this design is expected to be one of the most practical multiple-valued mask-ROM's.

This report describes 4-2 compressors composed of Complementary Pass-Transistor Logic (CPL). We will show that circuit designs of the 4-2 compressors can be optimized for high speed and small size using only exclusive-OR's and multiplexers. According to a circuit simulation with 0.8µm CMOS device parameters, the maximum propagation delay and the average power consumption per unit adder are 1.32 ns and 11.6 pJ, respectively.