IEICE TRANSACTIONS on Fundamentals
Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization
Summary :
In several design methods for Pass-transistor Logic (PTL) circuits, Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper, we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.
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- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.11 pp.2407-2413
- Publication Date
- 1999/11/25
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- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Kazuyoshi TAKAGI, Hiroshi HATAKEDA, Shinji KIMURA, Katsumasa WATANABE, "Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2407-2413, November 1999, doi: .
Abstract: In several design methods for Pass-transistor Logic (PTL) circuits, Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper, we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2407/_p
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@ARTICLE{e82-a_11_2407,
author={Kazuyoshi TAKAGI, Hiroshi HATAKEDA, Shinji KIMURA, Katsumasa WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization},
year={1999},
volume={E82-A},
number={11},
pages={2407-2413},
abstract={In several design methods for Pass-transistor Logic (PTL) circuits, Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper, we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2407
EP - 2413
AU - Kazuyoshi TAKAGI
AU - Hiroshi HATAKEDA
AU - Shinji KIMURA
AU - Katsumasa WATANABE
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - In several design methods for Pass-transistor Logic (PTL) circuits, Boolean functions are expressed as OBDDs in decomposed form and then the component OBDDs are directly mapped to PTL cells. The total size of OBDDs (number of nodes) corresponds to the circuit size. In this paper, we investigate a method for PTL synthesis based on exact minimization of Free BDDs (FBDDs). FBDDs are well-studied extension of OBDDs with free variable ordering on each path. We present statistics showing that more than 56% of 616126 NPN-equivalence classes of 5-variable Boolean functions have minimum FBDDs with less size than their OBDDs. This result can be used for PTL synthesis as libraries. We also applied the exact minimization algorithm of FBDDs to the minimization of subcircuits in the synthesis for MCNC benchmarks and found up to 5% size reduction.
ER -
English
