A novel high speed 4-2 compressor using static and pass-transistor logic, has been designed in a 0.35 µm CMOS technology. In order to reduce gate level delay and increase the speed, some changes are performed in truth table of conventional 4-2 compressor which leaded to the simplification of logic function for all parameters. Therefore, power dissipation is decreased. In addition, because of similar paths from all inputs to the outputs, the delays are the same. So there will be no need for extra buffers in low latency paths to equalize the delays.

High-Speed High-Resolution Comparators are integral parts of very high-speed high-resolution Analog-to-Digital Converters (ADC). Parallel successive-approximation and flash ADCS can boost conversion rates while providing high resolution, provided that accurate and fast offset-cancelled comparators could be implemented. Moreover, accurate offset cancellation is needed in accurate gain stages of other types of high speed ADCs as well. This has never been easy and creates a bottle neck for high-speed high-resolution ADCs. The reason is that conventional offset cancellation methods, suffer either from inaccurate cancellation or from slow operation. Hence, either speed or accuracy is compromised. This is due to the trade off of gain (accuracy) for bandwidth (speed) in conventional methods. Here, we introduce a new offset cancellation method which satisfies the need for both high-speed and accurate offset cancellation simultaneously.

In this paper, a new full on-chip high efficiency DC-DC voltage up converter with no inductance element is presented with power efficiency more than 74%. A method in the charge pump is described to have a regulated 3.3 V from 1.5 V for output power 4 mW. For medium power class, 100-200 mW, a boost converter is designed with on-chip inductor for 1.5 V to 3.3 V conversion. A buck converter is also designed for 3.3 V to 1 V conversion with power efficiency 72%. Inductor property of bond-wire is employed in the on-chip inductors. Analysis of efficiency relations and simulation results are presented for 0.35 µm CMOS technology.

This paper presents a new Fuzzy Logic Controller (FLC) having the ability to support rational-powered membership functions. These functions are extended forms of triangular/trapezoidal membership functions, and also those functions which are generated by applying linguistic hedges. A two-input, single-output, nine-rule Takagi-Sugeno-Kang (TSK) type FLC is designed in 0.35 µm standard CMOS technology. This controller can also be used as a standard (Mamdani) type FLC having singleton output membership functions, as well as a Linguistic Hedge FLC (LHFLC). Mixed analog/digital realization of the circuit makes the design programmable and extendable, while having relatively low power consumption. Current mode realization of the circuits leads to simple and intuitive configurations. For a particular set of programming parameters, simulation results of the controller using HSPICE simulator and level 49 parameters (BSIM3v3), show an average power consumption of 5 mW, and an RMS error of 1.32% compared to ideal results obtained from MATLAB software.

A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 µm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consumption and die area are 0.6 mW and 0.95 mm2, respectively. ADC was extensively simulated using Hspice to verify the desired performance.

This paper describes a new special purpose Variable Gain Amplifier (VGA) using 0.5µm digital CMOS process. The new architecture allows the gain to be varied more than 20dB, and does not trade bandwidth for gain. Despite low power consumption (22mW) from a 3.3 Volt supply, the circuit has 310MHz -3dB bandwidth and shows low THD (-45dB) over its full frequency range. The new VGA architecture does not use any capacitor or resistor array for gain adjustment, thus it is very compact (0.14mm 0.26mm) and requires less power than conventional designs.

In this paper, a new operational amplifier is presented that improves the specifications such as dc gain, common mode rejection ratio. To obtain these improvements, we have used the two important concepts of feedback and bulk amplification.

This paper presents a novel gain boosted and bandwidth enhanced CMOS Op-Amp based on the well-known folded cascode structure. In contrast with the conventional methods which increase output resistance for gain boosting, the transconductance of the circuit is increased, therefore the -3 dB frequency is the same as for folded cascode structure. With negligible extra power consumption, the unity gain bandwidth is increased considerably. In this method, a new node is created in the circuit which introduces a pole to the transfer function with a frequency lower than cascode pole; feed-forward compensation is employed to reduce the effect of this pole on the frequency response. The input common mode range is limited slightly by 0.2-0.3 V with respect to folded cascode which is insensible. HSPICE simulations using level 49 parameters (BSIM3v3) in a typical 0.35 µm CMOS technology result in three times gain boosting and 60% enhancement in unity gain bandwidth compared to folded cascode, while the power consumption is increased by 10%.

This article describes a large bandwidth and low distortion line driver in a 0.35-µm CMOS process. The line driver drives a 75 Ω resistive load. Its power consumption is 140 mW from a 3.3 V supply. It has a relatively high -3 dB bandwidth (260 MHz) with good phase margin of about 70 degrees. It shows very low THD (-74.5 dB) when drives the load with a 3.3 V peak to peak sine wave at 10 MHz. This architecture reduces the distortion by locating the input differential pair inside the feedback loop and eliminating the distortion of the feedback transistors, which is dominant source of distortion at high frequencies. Thus, it improves the linearity of the output voltage in comparison with previous designs.

This paper presents design of a novel high speed booth encoder-decoder in a 0.35 µm CMOS technology. Focusing on transistor level implementation of the new architecture and employing newly designed truth table, the gate level delay of the whole system is reduced to one logic gate plus one transistor delay which is the main advantage of the proposed circuit. Simulation results indicate high speed performance of the designed circuit and depict low power dissipation feature of implemented architecture which makes this work suitable for extensive use in high speed arithmetic blocks.

This paper presents a new open-loop phase shifter and frequency synthesizer which can be implemented by small hardware. In the proposed method the differential square wave is converted to a differential ramp. Then the cross points of two ramps are detected as the middle points of high or low durations and are recovered to full digital levels, for 90shifting operation. 4-phases in 50 MHz frequency can be generated by 3.5 mW power consumption and 60 µm60 µm area. All circuits have been simulated in 0.35 µm CMOS technology.

This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.

A CMOS circuit is proposed which takes multiple analog input currents and extracts minimum input current at the output. It is very fast and requires no subtraction from the constant current source. It exhibits O(N) complexity and uses only 4N MOS transistors where N is the number of system inputs. This circuit consumes very little power and very small area. The substrate bias affects the threshold voltage of transistors and improves performance of the structure.

In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.