A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 µm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consumption and die area are 0.6 mW and 0.95 mm2, respectively. ADC was extensively simulated using Hspice to verify the desired performance.