Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations
Summary :
This paper presents design of a novel high speed booth encoder-decoder in a 0.35 µm CMOS technology. Focusing on transistor level implementation of the new architecture and employing newly designed truth table, the gate level delay of the whole system is reduced to one logic gate plus one transistor delay which is the main advantage of the proposed circuit. Simulation results indicate high speed performance of the designed circuit and depict low power dissipation feature of implemented architecture which makes this work suitable for extensive use in high speed arithmetic blocks.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.4 pp.706-709
- Publication Date
- 2012/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.706
- Type of Manuscript
- BRIEF PAPER
- Category
Authors
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Amir FATHI, Sarkis AZIZIAN, Khayrollah HADIDI, Abdollah KHOEI, "Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 4, pp. 706-709, April 2012, doi: 10.1587/transele.E95.C.706.
Abstract: This paper presents design of a novel high speed booth encoder-decoder in a 0.35 µm CMOS technology. Focusing on transistor level implementation of the new architecture and employing newly designed truth table, the gate level delay of the whole system is reduced to one logic gate plus one transistor delay which is the main advantage of the proposed circuit. Simulation results indicate high speed performance of the designed circuit and depict low power dissipation feature of implemented architecture which makes this work suitable for extensive use in high speed arithmetic blocks.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.706/_p
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@ARTICLE{e95-c_4_706,
author={Amir FATHI, Sarkis AZIZIAN, Khayrollah HADIDI, Abdollah KHOEI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations},
year={2012},
volume={E95-C},
number={4},
pages={706-709},
abstract={This paper presents design of a novel high speed booth encoder-decoder in a 0.35 µm CMOS technology. Focusing on transistor level implementation of the new architecture and employing newly designed truth table, the gate level delay of the whole system is reduced to one logic gate plus one transistor delay which is the main advantage of the proposed circuit. Simulation results indicate high speed performance of the designed circuit and depict low power dissipation feature of implemented architecture which makes this work suitable for extensive use in high speed arithmetic blocks.},
keywords={},
doi={10.1587/transele.E95.C.706},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations
T2 - IEICE TRANSACTIONS on Electronics
SP - 706
EP - 709
AU - Amir FATHI
AU - Sarkis AZIZIAN
AU - Khayrollah HADIDI
AU - Abdollah KHOEI
PY - 2012
DO - 10.1587/transele.E95.C.706
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2012
AB - This paper presents design of a novel high speed booth encoder-decoder in a 0.35 µm CMOS technology. Focusing on transistor level implementation of the new architecture and employing newly designed truth table, the gate level delay of the whole system is reduced to one logic gate plus one transistor delay which is the main advantage of the proposed circuit. Simulation results indicate high speed performance of the designed circuit and depict low power dissipation feature of implemented architecture which makes this work suitable for extensive use in high speed arithmetic blocks.
ER -
English
