This paper describes a method to evaluate the modulated waveforms output by a high-speed external phase modulator over a wide wavelength range by using linear optical sampling (LOS) and a wavelength-swept light source. The phase-modulated waveform is sampled by LOS together with the reference signal before modulation, and the modulation waveform is observed by removing the phase noise of the light source extracted from the reference signal. In this process, the frequency offset caused by the optical-path length difference between the measurement and reference interferometers is removed by digital signal processing. A pseudo-random binary-sequence modulated signal is observed with a temporal resolution of 10ps. We obtained a dynamic range of ∼40dB for the measurement bandwidth of 10 nm. When the measurement bandwidth is expanded to entire C-Band (∼35nm), the dynamic ranges of 37∼46dB were observed, depending on the wavelengths. The measurement time was sub-seconds throughout the experiment.

In order to enhance the fifth generation (5G) mobile communication system further toward 5G Evolution, high bit-rate transmission using high SHF bands (28GHz or EHF bands) should be more stable even in high-mobility environments such as high speed trains. Of particular importance, dynamic changes in the beam direction and the larger Doppler frequency shift can degrade transmission performances in such high frequency bands. Thus, we conduct the world's first 28 GHz-band 5G experimental trial on an actual Shinkansen running at a speed of 283km/h in Japan. This paper introduces the 28GHz-band experimental system used in the 5G experimental trial using the Shinkansen, and then it presents the experimental configuration in which three base stations (BSs) are deployed along the Tokaido Shinkansen railway and a mobile station is located in the train. In addition, transmission performances measured in this ultra high-mobility environment, show that a peak throughput of exceeding 1.0Gbps and successful consecutive BS connection among the three BSs.

Silver electrical contacts were separated at constant opening speed in a 200V-500VDC/10A resistive circuit. Break arcs were extinguished by magnetic blowing-out with transverse magnetic field of a permanent magnet. The permanent magnet was appropriately located to simplify the lengthened shape of the break arcs. Magnetic flux density of the transverse magnetic field was varied from 20 to 140mT. Images of the break arcs were observed from the horizontal and vertical directions using two high speed cameras simultaneously. Arc length just before extinction was analyzed from the observed images. It was shown that shapes of the break arcs were simple enough to trace the most part of paths of the break arcs for all experimental conditions owing to simplification of the shapes of the break arcs by appropriate arrangement of the magnet. The arc length increased with increasing supply voltage and decreased with increasing magnetic flux density. These results will be discussed in the view points of arc lengthening time and arc lengthening velocity.

We propose a non-photorealistic rendering method for generating edge-preserving bubble images from gray-scale photographic images. Bubble images are non-photorealistic images embedded in many bubbles, and edge-preserving bubble images are bubble images where edges in photographic images are preserved. The proposed method is executed by an iterative processing using absolute difference in window. The proposed method has features that processing is simple and fast. To validate the effectiveness of the proposed method, experiments using various photographic images are conducted. Results show that the proposed method can generate edge-preserving bubble images by preserving the edges of photographic images and the processing speed is high.

Many applications, such as image signal processing, has an inherent tolerance for insignificant inaccuracies. Multiplication is a key arithmetic function for many applications. Approximate multipliers are considered an efficient technique to trade off energy relative to performance and accuracy for the error-tolerant applications. Here, we design and analyze four approximate multipliers that demonstrate lower power consumption and shorter critical path delay than the conventional multiplier. They employ an approximate tree compressor that halves the height of the partial product tree and generates a vector to compensate accuracy. Compared with the conventional Wallace tree multiplier, one of the evaluated 8-bit approximate multipliers reduces power consumption and critical path delay by 36.9% and 38.9%, respectively. With a 0.25% normalized mean error distance, the silicon area required to implement the multiplier is reduced by 50.3%. Our multipliers outperform the previously proposed approximate multipliers relative to power consumption, critical path delay, and design area. Results from two image processing applications also demonstrate that the qualities of the images processed by our multipliers are sufficiently accurate for such error-tolerant applications.

Electrical contacts are separated at constant speed and break arcs are generated in nitrogen or air in a 200V-450VDC/10A resistive circuit. The break arcs are extinguished by magnetic blow-out. Arc duration for the silver and copper contact pairs is investigated for each supply voltage. Following results are shown. The arc duration for Cu contacts in nitrogen is the shortest. For Cu contacts, the arc dwell time in air was considerably longer than that of nitrogen. For Ag contacts, the arc duration in nitrogen was almost the same as that in air.

This paper presents a novel method for unsupervised segmentation of objects with large displacements in high speed video sequences. Our general framework introduces a new foreground object predicting method that finds object hypotheses by encoding both spatial and temporal features via a semantic motion signature scheme. More specifically, temporal cues of object hypotheses are captured by the motion signature proposed in this paper, which is derived from sparse saliency representation imposed on magnitude of optical flow field. We integrate semantic scores derived from deep networks with location priors that allows us to directly estimate appearance potentials of foreground hypotheses. A unified MRF energy functional is proposed to simultaneously incorporate the information from the motion signature and semantic prediction features. The functional enforces both spatial and temporal consistency and impose appearance constancy and spatio-temporal smoothness constraints directly on the object hypotheses. It inherently handles the challenges of segmenting ambiguous objects with large displacements in high speed videos. Our experiments on video object segmentation benchmarks demonstrate the effectiveness of the proposed method for segmenting high speed objects despite the complicated scene dynamics and large displacements.

Silver electrical contacts are separated at constant speed and break arcs are generated between them in a 200V-450VDC and 10A resistive circuit. The motion of the break arcs is restricted by some surrounding alumina plates. Transverse magnetic field of a permanent magnet is applied to the break arcs. Changing the supply voltage and the height of a wall located at the upper side of the break arcs, the arc lengthening time and motion of the break arcs are investigated. As a result, the higher supply voltage causes an increase of the arc lengthening time. The arc lengthening time increases significantly when the break arcs expand into the whole of the surrounding walls.

Silver contacts are separated at constant speed and break arcs are generated in a 300V-450V DC and 10A resistive circuit. The transverse magnetic field of a permanent magnet is applied to the break arcs. Motion of the break arcs, arc duration and the number of reignitions are investigated when side surfaces of the contacts are covered with insulator pipes. Following results are shown. The motion of the break arcs and the arc duration when the anode is covered with the pipe are the same as those without pipes. When the cathode is covered with the pipe, the motion of break arcs change from that without the pipes and reignitions occur more frequently. The arc duration becomes longer than that without the pipes because of the occurrence of reignitions. The number of reignition increases with increasing the supply voltage in 300V-400V. The period of occurrence of the reignition with pipes is shorter than that when the cathode is covered with the pipe.

Two-port SRAMs are frequently installed in gate-array VLSIs to implement smart functions. This paper presents a new high-density 10T CMOS base cell for gate-array-based two-port SRAM applications. Using the single base cell alone, we can implement a two-port memory cell whose bitline contacts are shared with the memory cell adjacent to one of two dedicated sides, resulting in greatly reduced parasitic capacitance in bitlines. To throw light on the total performance derived from the base cell, a plain two-port SRAM macro was designed and fabricated with a 0.35-µm low cost, logic process. Each of two 10-bit power-saved address decoders was formed with 36% fewer base cells by employing complex gates and a subdecoder. The new sense amplifier with a complementary sensing scheme had a fine sensitivity of 35 mVpp, and so we successfully reduced the required read bitline signal from 250 to 70 mVpp. With the macro with 1024 memory cells per bitline, the address access time under typical conditions of a 2.5-V power supply and 25°C was 4.0 ns (equal to that obtained with full-custom style design) and the power consumption at 200-MHz simultaneous operations of two ports was 6.7 mW for an I/O-data width of 1 bit.

This paper introduces low-power and small area injection-locking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2- V supply at 12.5Gbps. The fabricated CDR achieved a BER lower than 10-12 and the recovered clock had an rms jitter of 0.87ps. The CDR area is 0.165mm2.

With the growth of cloud-based services, cloud data centers are experiencing large growth. A key component in a cloud data center is the network technology deployed. In particular, Ethernet technology, commonly deployed in cloud data centers, is already envisioned for 10 Tbps Ethernet. In this paper, we study and analyze the makespan, workload execution times, and virtual machine migrations as the network speed increases. In particular, we consider homogeneous and heterogeneous data centers, virtual machine scheduling algorithms, and workload scheduling algorithms. Results obtained from our study indicate that the increase in a network's speed reduces makespan and workloads execution times, while aiding in the increase of the number of virtual machine migrations. We further observed that the number of migrations' behaviors in relation to the speed of the networks also depends on the employed virtual machines scheduling algorithm.

We propose a current mode sense amplifier that uses a current-mirror to increase the bitline sensing current, which dominates the sensing speed. A comparison of the sensing delay shows that the proposed sense amplifier can provide about 12.6∼15.4% improvement depending on different bitline loads in sensing speed over original WTA scheme.

Facial micro-expressions are fast and subtle facial motions that are considered as one of the most useful external signs for detecting hidden emotional changes in a person. However, they are not easy to detect and measure as they appear only for a short time, with small muscle contraction in the facial areas where salient features are not available. We propose a new computer vision method for detecting and measuring timing characteristics of facial micro-expressions. The core of this method is based on a descriptor that combines pre-processing masks, histograms and concatenation of spatial-temporal gradient vectors. Presented 3D gradient histogram descriptor is able to detect and measure the timing characteristics of the fast and subtle changes of the facial skin surface. This method is specifically designed for analysis of videos recorded using a hi-speed 200 fps camera. Final classification of micro expressions is done by using a k-mean classifier and a voting procedure. The Facial Action Coding System was utilized to annotate the appearance and dynamics of the expressions in our new hi-speed micro-expressions video database. The efficiency of the proposed approach was validated using our new hi-speed video database.

A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.

This paper presents design of a novel high speed booth encoder-decoder in a 0.35 µm CMOS technology. Focusing on transistor level implementation of the new architecture and employing newly designed truth table, the gate level delay of the whole system is reduced to one logic gate plus one transistor delay which is the main advantage of the proposed circuit. Simulation results indicate high speed performance of the designed circuit and depict low power dissipation feature of implemented architecture which makes this work suitable for extensive use in high speed arithmetic blocks.

The charge-redistribution low-swing differential logic (CLDL) circuits are presented in this work. It can implement a complex function in a single gate. The CLDL circuits utilizes the charge-redistribution and reduced-swing schemes to reduce the power dissipation and enhance the operation speed. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. The CLDL circuits perform more than 25% speedup and 31% in power-delay product compared to other differential circuits with true-single-phase clock. A pipelined multiplier-accumulator (MAC) using CLDL structure is fabricated in 0.35 µm single-poly four-metal CMOS process. The test chip is successfully verified to operate at 900-MHz.

This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.

High luminance and high speed response with the cut-off frequency of more than 50 MHz in multilayer polyfluorene-based light-emitting diodes with an interlayer were achieved. We realized multilayer polyfluorene-based light-emitting diodes for frequency response up to 100 MHz.

Substrate noise analysis has become increasingly important in recent LSI design. This is because substrate noise, which affects PLLs, causes jitter that results in timing error. Conventional analysis techniques of substrate noise are, however, impractical for large-scale designs that have hundreds of millions of transistors because the computational complexity is too huge. To solve this problem, we have developed a fast substrate noise analysis technique for large-scale designs, in which a chip is divided into multiple domains and the circuits of each domain are reduced into a macro model. Using this technique, we have designed a processor chip for use in the supercomputer (die size: 20 mm 21 mm, frequency: 3.2 GHz, transistor count: 350M). Computation time with this design is five times faster than that with a 1/3000 scale design using a conventional technique, while resulting discrepancy with measured period jitter is less than 15%.