IEICE TRANSACTIONS on Electronics
A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF)
Summary :
A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.6 pp.1125-1127
- Publication Date
- 2012/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.1125
- Type of Manuscript
- BRIEF PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Xiayu LI, Song JIA, Limin LIU, Yuan WANG, "A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF)" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 6, pp. 1125-1127, June 2012, doi: 10.1587/transele.E95.C.1125.
Abstract: A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1125/_p
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@ARTICLE{e95-c_6_1125,
author={Xiayu LI, Song JIA, Limin LIU, Yuan WANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF)},
year={2012},
volume={E95-C},
number={6},
pages={1125-1127},
abstract={A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.},
keywords={},
doi={10.1587/transele.E95.C.1125},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF)
T2 - IEICE TRANSACTIONS on Electronics
SP - 1125
EP - 1127
AU - Xiayu LI
AU - Song JIA
AU - Limin LIU
AU - Yuan WANG
PY - 2012
DO - 10.1587/transele.E95.C.1125
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2012
AB - A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.
ER -
English
