Information security has been seriously threatened by the differential power analysis (DPA). Delay-based dual-rail precharge logic (DDPL) is an effective solution to resist these attacks. However, conventional DDPL convertors have some shortcomings. In this paper, we propose improved convertor pairs based on dynamic logic and a sense amplifier (SA). Compared with the reference CMOS-to-DDPL convertor, our scheme could save 69% power consumption. As to the comparison of DDPL-to-CMOS convertor, the speed and power performances could be improved by 39% and 54%, respectively.

We newly propose the first lateral mode selective active multimode interferometer laser diode. The design principle is to arrange identical propagation path of different lateral mode. Thanks to multimode waveguide structure, 0th mode and 1st order mode has individual propagation path within one device. Individual lasing of fundamental mode as well as first mode was confirmed successfully.

We propose a current mode sense amplifier that uses a current-mirror to increase the bitline sensing current, which dominates the sensing speed. A comparison of the sensing delay shows that the proposed sense amplifier can provide about 12.6∼15.4% improvement depending on different bitline loads in sensing speed over original WTA scheme.

A novel shuffle converter by using 3D waveguide of MCF (multi-core fiber)/SMF (single mode fiber) ribbon fan-in fan-out configuration towards over 1,000 port count optical matrix switch has been proposed. The shuffle converter enables to avoid waveguide crossing section in the optical matrix switch configuration, and the principle device showed sufficient crosstalk of less than -54.2 dB, and insertion loss of 2.1 dB successfully.

Side channel attacks (SCAs) on security devices have become a major concern for system security. Existing SCA countermeasures are costly in terms of area and power consumption. This paper presents a novel differential power analysis (DPA) countermeasure referred to as short-time three-phase single-rail precharge logic (STSPL). The proposed logic is based on a single-rail three-phase operation scheme providing effective DPA-resistance with low cost. In the scheme, a controller is inserted to discharge logic gates by reusing evaluation paths to achieve more balanced power consumption. This reduces the latency between different phases, increasing the difficult of the adversary to conduct DPA, compared with the state-of-the-art DPA-resistance logics. To verify the chip's power consumption in practice, a 4-bit ripple carry adder and a 4-bit inverter of AES-SBOX were implemented. The testing and simulation results of DPA attacks prove the security and efficiency of the proposed logic.

We present dynamic mode switching characteristic by using a 2 × 2 optical mode switch based on silicon waveguide. The configuration of optical mode switch is similar to MZI where the width of input and output ports are designed to permit the combining of the fundamental mode and the first order mode. We designed the symmetrical arms with phase shifter based on p-i-n structure in one arm to generate a π-phase difference between each arm. As a result, mode switching with the injection current of 60mA (5.7V) was successfully achieved with the mode crosstalk of -10dB at λ=1550nm. A minimum of less than 60ns and 40ns mode switching time for the fundamental mode to first order mode and first order mode to fundamental mode, was achieved respectively in this time.

We have proposed and demonstrated the principle of optical mode switch. However, the crosstalk between modes has not yet reported due to the difficulty of mode recognition and distinction. To accomplish this mode crosstalk evaluation, we integrated multimode interference (MMI) mode filter with the optical mode switch in this work. As a result, for the both TE and TM modes, the crosstalk of approximately -10 dB has been evaluated experimentally.

Serial RapidIO (SRIO) is a high-performance interconnection standard for embedded systems. Cyclic Redundancy Check (CRC) provides protection for packet transmissions and impacts the device performances. In this paper, two CRC calculation strategies, based on adjustable slicing parallelization and simplified calculators, are proposed. In the first scheme, the temporary CRC result of the previous cycle (CPre) is considered as a dependent input for the new cycle and is combined with a specific segment of packet data before slicing parallelization. In the second scheme, which can reach a higher maximum working frequency, CPre is considered as an independent input and is separated from the calculation of packet data for further parallelization. Performance comparisons based on ASIC and FPGA implementations are demonstrated to show their effectiveness. Compared with the reference designs, more than 34.8% and 13.9% of average power can be improved by the two proposed schemes at 156.25MHz in 130nm technology, respectively.

This paper reports a single dimensional mode based multiplexer / de-multiplexer using the slab waveguide to realize high modes multiplexing and high integration in the non-MIMO (multi-in multi-out) multimode transmission system. A sufficient mode crosstalk of -20 dB was obtained by selecting suitable parameters of the spacing between the connecting positions of each arrayed waveguide Di, the radius slab waveguide R0 and lateral V-parameter.

A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.

We have proposed and demonstrated a mode selective active-MMI (multimode interferometer) laser diode as a mode selective light source so far. This laser diode features; 1) lasing at a selected space mode, and 2) high modulation bandwidth. Based on these, it is expected to enable high speed interconnection into future personal and mobile devices. In this paper, we explain the mode selection, and the high speed modulation principles. Then, we present our recent results concerning high speed frequency response of the fundamental and first order space modes.