IEICE TRANSACTIONS on Electronics
A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis
Summary :
Side channel attacks (SCAs) on security devices have become a major concern for system security. Existing SCA countermeasures are costly in terms of area and power consumption. This paper presents a novel differential power analysis (DPA) countermeasure referred to as short-time three-phase single-rail precharge logic (STSPL). The proposed logic is based on a single-rail three-phase operation scheme providing effective DPA-resistance with low cost. In the scheme, a controller is inserted to discharge logic gates by reusing evaluation paths to achieve more balanced power consumption. This reduces the latency between different phases, increasing the difficult of the adversary to conduct DPA, compared with the state-of-the-art DPA-resistance logics. To verify the chip's power consumption in practice, a 4-bit ripple carry adder and a 4-bit inverter of AES-SBOX were implemented. The testing and simulation results of DPA attacks prove the security and efficiency of the proposed logic.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.8 pp.956-962
- Publication Date
- 2016/08/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.956
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Wenyi TANG
Peking University
Song JIA
Peking University
Yuan WANG
Peking University
Keyword
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Wenyi TANG, Song JIA, Yuan WANG, "A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 8, pp. 956-962, August 2016, doi: 10.1587/transele.E99.C.956.
Abstract: Side channel attacks (SCAs) on security devices have become a major concern for system security. Existing SCA countermeasures are costly in terms of area and power consumption. This paper presents a novel differential power analysis (DPA) countermeasure referred to as short-time three-phase single-rail precharge logic (STSPL). The proposed logic is based on a single-rail three-phase operation scheme providing effective DPA-resistance with low cost. In the scheme, a controller is inserted to discharge logic gates by reusing evaluation paths to achieve more balanced power consumption. This reduces the latency between different phases, increasing the difficult of the adversary to conduct DPA, compared with the state-of-the-art DPA-resistance logics. To verify the chip's power consumption in practice, a 4-bit ripple carry adder and a 4-bit inverter of AES-SBOX were implemented. The testing and simulation results of DPA attacks prove the security and efficiency of the proposed logic.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.956/_p
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@ARTICLE{e99-c_8_956,
author={Wenyi TANG, Song JIA, Yuan WANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis},
year={2016},
volume={E99-C},
number={8},
pages={956-962},
abstract={Side channel attacks (SCAs) on security devices have become a major concern for system security. Existing SCA countermeasures are costly in terms of area and power consumption. This paper presents a novel differential power analysis (DPA) countermeasure referred to as short-time three-phase single-rail precharge logic (STSPL). The proposed logic is based on a single-rail three-phase operation scheme providing effective DPA-resistance with low cost. In the scheme, a controller is inserted to discharge logic gates by reusing evaluation paths to achieve more balanced power consumption. This reduces the latency between different phases, increasing the difficult of the adversary to conduct DPA, compared with the state-of-the-art DPA-resistance logics. To verify the chip's power consumption in practice, a 4-bit ripple carry adder and a 4-bit inverter of AES-SBOX were implemented. The testing and simulation results of DPA attacks prove the security and efficiency of the proposed logic.},
keywords={},
doi={10.1587/transele.E99.C.956},
ISSN={1745-1353},
month={August},}
Copy
TY - JOUR
TI - A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis
T2 - IEICE TRANSACTIONS on Electronics
SP - 956
EP - 962
AU - Wenyi TANG
AU - Song JIA
AU - Yuan WANG
PY - 2016
DO - 10.1587/transele.E99.C.956
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2016
AB - Side channel attacks (SCAs) on security devices have become a major concern for system security. Existing SCA countermeasures are costly in terms of area and power consumption. This paper presents a novel differential power analysis (DPA) countermeasure referred to as short-time three-phase single-rail precharge logic (STSPL). The proposed logic is based on a single-rail three-phase operation scheme providing effective DPA-resistance with low cost. In the scheme, a controller is inserted to discharge logic gates by reusing evaluation paths to achieve more balanced power consumption. This reduces the latency between different phases, increasing the difficult of the adversary to conduct DPA, compared with the state-of-the-art DPA-resistance logics. To verify the chip's power consumption in practice, a 4-bit ripple carry adder and a 4-bit inverter of AES-SBOX were implemented. The testing and simulation results of DPA attacks prove the security and efficiency of the proposed logic.
ER -
English
