IEICE TRANSACTIONS on Electronics
Improved CRC Calculation Strategies for 64-bit Serial RapidIO
Summary :
Serial RapidIO (SRIO) is a high-performance interconnection standard for embedded systems. Cyclic Redundancy Check (CRC) provides protection for packet transmissions and impacts the device performances. In this paper, two CRC calculation strategies, based on adjustable slicing parallelization and simplified calculators, are proposed. In the first scheme, the temporary CRC result of the previous cycle (CPre) is considered as a dependent input for the new cycle and is combined with a specific segment of packet data before slicing parallelization. In the second scheme, which can reach a higher maximum working frequency, CPre is considered as an independent input and is separated from the calculation of packet data for further parallelization. Performance comparisons based on ASIC and FPGA implementations are demonstrated to show their effectiveness. Compared with the reference designs, more than 34.8% and 13.9% of average power can be improved by the two proposed schemes at 156.25MHz in 130nm technology, respectively.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.10 pp.1330-1338
- Publication Date
- 2013/10/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.1330
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Fengfeng WU
IME, PKU
Song JIA
IME, PKU
Qinglong MENG
IME, PKU
Shigong LV
IME, PKU
Yuan WANG
IME, PKU
Dacheng ZHANG
IME, PKU
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Fengfeng WU, Song JIA, Qinglong MENG, Shigong LV, Yuan WANG, Dacheng ZHANG, "Improved CRC Calculation Strategies for 64-bit Serial RapidIO" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 10, pp. 1330-1338, October 2013, doi: 10.1587/transele.E96.C.1330.
Abstract: Serial RapidIO (SRIO) is a high-performance interconnection standard for embedded systems. Cyclic Redundancy Check (CRC) provides protection for packet transmissions and impacts the device performances. In this paper, two CRC calculation strategies, based on adjustable slicing parallelization and simplified calculators, are proposed. In the first scheme, the temporary CRC result of the previous cycle (CPre) is considered as a dependent input for the new cycle and is combined with a specific segment of packet data before slicing parallelization. In the second scheme, which can reach a higher maximum working frequency, CPre is considered as an independent input and is separated from the calculation of packet data for further parallelization. Performance comparisons based on ASIC and FPGA implementations are demonstrated to show their effectiveness. Compared with the reference designs, more than 34.8% and 13.9% of average power can be improved by the two proposed schemes at 156.25MHz in 130nm technology, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.1330/_p
Copy
@ARTICLE{e96-c_10_1330,
author={Fengfeng WU, Song JIA, Qinglong MENG, Shigong LV, Yuan WANG, Dacheng ZHANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Improved CRC Calculation Strategies for 64-bit Serial RapidIO},
year={2013},
volume={E96-C},
number={10},
pages={1330-1338},
abstract={Serial RapidIO (SRIO) is a high-performance interconnection standard for embedded systems. Cyclic Redundancy Check (CRC) provides protection for packet transmissions and impacts the device performances. In this paper, two CRC calculation strategies, based on adjustable slicing parallelization and simplified calculators, are proposed. In the first scheme, the temporary CRC result of the previous cycle (CPre) is considered as a dependent input for the new cycle and is combined with a specific segment of packet data before slicing parallelization. In the second scheme, which can reach a higher maximum working frequency, CPre is considered as an independent input and is separated from the calculation of packet data for further parallelization. Performance comparisons based on ASIC and FPGA implementations are demonstrated to show their effectiveness. Compared with the reference designs, more than 34.8% and 13.9% of average power can be improved by the two proposed schemes at 156.25MHz in 130nm technology, respectively.},
keywords={},
doi={10.1587/transele.E96.C.1330},
ISSN={1745-1353},
month={October},}
Copy
TY - JOUR
TI - Improved CRC Calculation Strategies for 64-bit Serial RapidIO
T2 - IEICE TRANSACTIONS on Electronics
SP - 1330
EP - 1338
AU - Fengfeng WU
AU - Song JIA
AU - Qinglong MENG
AU - Shigong LV
AU - Yuan WANG
AU - Dacheng ZHANG
PY - 2013
DO - 10.1587/transele.E96.C.1330
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2013
AB - Serial RapidIO (SRIO) is a high-performance interconnection standard for embedded systems. Cyclic Redundancy Check (CRC) provides protection for packet transmissions and impacts the device performances. In this paper, two CRC calculation strategies, based on adjustable slicing parallelization and simplified calculators, are proposed. In the first scheme, the temporary CRC result of the previous cycle (CPre) is considered as a dependent input for the new cycle and is combined with a specific segment of packet data before slicing parallelization. In the second scheme, which can reach a higher maximum working frequency, CPre is considered as an independent input and is separated from the calculation of packet data for further parallelization. Performance comparisons based on ASIC and FPGA implementations are demonstrated to show their effectiveness. Compared with the reference designs, more than 34.8% and 13.9% of average power can be improved by the two proposed schemes at 156.25MHz in 130nm technology, respectively.
ER -
English
