IEICE TRANSACTIONS on Electronics
A 500 MS/s 600 µW 300 µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process
Summary :
This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.4 pp.635-640
- Publication Date
- 2011/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.635
- Type of Manuscript
- BRIEF PAPER
- Category
Authors
Keyword
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Sarang KAZEMINIA, Morteza MOUSAZADEH, Kayrollah HADIDI, Abdollah KHOEI, "A 500 MS/s 600 µW 300 µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 635-640, April 2011, doi: 10.1587/transele.E94.C.635.
Abstract: This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.635/_p
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@ARTICLE{e94-c_4_635,
author={Sarang KAZEMINIA, Morteza MOUSAZADEH, Kayrollah HADIDI, Abdollah KHOEI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 500 MS/s 600 µW 300 µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process},
year={2011},
volume={E94-C},
number={4},
pages={635-640},
abstract={This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.},
keywords={},
doi={10.1587/transele.E94.C.635},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - A 500 MS/s 600 µW 300 µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process
T2 - IEICE TRANSACTIONS on Electronics
SP - 635
EP - 640
AU - Sarang KAZEMINIA
AU - Morteza MOUSAZADEH
AU - Kayrollah HADIDI
AU - Abdollah KHOEI
PY - 2011
DO - 10.1587/transele.E94.C.635
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.
ER -
English
