Full Chip Circuit/Substrate Macro Modeling Method Which Controls the Analysis Accuracy and CPU Time by Using Current Density

Mikiko Sode TANAKA, Mikihiro KAJITA, Naoya NAKAYAMA, Satoshi NAKAMOTO

Summary :

Substrate noise analysis has become increasingly important in recent LSI design. This is because substrate noise, which affects PLLs, causes jitter that results in timing error. Conventional analysis techniques of substrate noise are, however, impractical for large-scale designs that have hundreds of millions of transistors because the computational complexity is too huge. To solve this problem, we have developed a fast substrate noise analysis technique for large-scale designs, in which a chip is divided into multiple domains and the circuits of each domain are reduced into a macro model. Using this technique, we have designed a processor chip for use in the supercomputer (die size: 20 mm 21 mm, frequency: 3.2 GHz, transistor count: 350M). Computation time with this design is five times faster than that with a 1/3000 scale design using a conventional technique, while resulting discrepancy with measured period jitter is less than 15%.

• Publication: IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.2 pp.448-455
• Publication Date: 2010/02/01
• Online ISSN: 1745-1337
• DOI: 10.1587/transfun.E93.A.448
• Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

Authors

Mikiko Sode TANAKA
Mikihiro KAJITA
Naoya NAKAYAMA
Satoshi NAKAMOTO

Keyword

substrate noise,  power supply noise,  substrate modeling,  clock jitter,  high speed