CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes
Summary :
The charge-redistribution low-swing differential logic (CLDL) circuits are presented in this work. It can implement a complex function in a single gate. The CLDL circuits utilizes the charge-redistribution and reduced-swing schemes to reduce the power dissipation and enhance the operation speed. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. The CLDL circuits perform more than 25% speedup and 31% in power-delay product compared to other differential circuits with true-single-phase clock. A pipelined multiplier-accumulator (MAC) using CLDL structure is fabricated in 0.35 µm single-poly four-metal CMOS process. The test chip is successfully verified to operate at 900-MHz.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.2 pp.275-283
- Publication Date
- 2012/02/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.275
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Hong-Yi HUANG, Shiun-Dian JAN, Yang CHOU, Cheng-Yu CHEN, "CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 2, pp. 275-283, February 2012, doi: 10.1587/transele.E95.C.275.
Abstract: The charge-redistribution low-swing differential logic (CLDL) circuits are presented in this work. It can implement a complex function in a single gate. The CLDL circuits utilizes the charge-redistribution and reduced-swing schemes to reduce the power dissipation and enhance the operation speed. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. The CLDL circuits perform more than 25% speedup and 31% in power-delay product compared to other differential circuits with true-single-phase clock. A pipelined multiplier-accumulator (MAC) using CLDL structure is fabricated in 0.35 µm single-poly four-metal CMOS process. The test chip is successfully verified to operate at 900-MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.275/_p
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@ARTICLE{e95-c_2_275,
author={Hong-Yi HUANG, Shiun-Dian JAN, Yang CHOU, Cheng-Yu CHEN, },
journal={IEICE TRANSACTIONS on Electronics},
title={CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes},
year={2012},
volume={E95-C},
number={2},
pages={275-283},
abstract={The charge-redistribution low-swing differential logic (CLDL) circuits are presented in this work. It can implement a complex function in a single gate. The CLDL circuits utilizes the charge-redistribution and reduced-swing schemes to reduce the power dissipation and enhance the operation speed. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. The CLDL circuits perform more than 25% speedup and 31% in power-delay product compared to other differential circuits with true-single-phase clock. A pipelined multiplier-accumulator (MAC) using CLDL structure is fabricated in 0.35 µm single-poly four-metal CMOS process. The test chip is successfully verified to operate at 900-MHz.},
keywords={},
doi={10.1587/transele.E95.C.275},
ISSN={1745-1353},
month={February},}
Copy
TY - JOUR
TI - CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes
T2 - IEICE TRANSACTIONS on Electronics
SP - 275
EP - 283
AU - Hong-Yi HUANG
AU - Shiun-Dian JAN
AU - Yang CHOU
AU - Cheng-Yu CHEN
PY - 2012
DO - 10.1587/transele.E95.C.275
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2012
AB - The charge-redistribution low-swing differential logic (CLDL) circuits are presented in this work. It can implement a complex function in a single gate. The CLDL circuits utilizes the charge-redistribution and reduced-swing schemes to reduce the power dissipation and enhance the operation speed. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. The CLDL circuits perform more than 25% speedup and 31% in power-delay product compared to other differential circuits with true-single-phase clock. A pipelined multiplier-accumulator (MAC) using CLDL structure is fabricated in 0.35 µm single-poly four-metal CMOS process. The test chip is successfully verified to operate at 900-MHz.
ER -
English
