IEICE TRANSACTIONS on Fundamentals
A Highly Linear and Large Bandwidth Fully Differential CMOS Line Driver Suitable for High-Speed Data Transmission Applications
Summary :
This article describes a large bandwidth and low distortion line driver in a 0.35-µm CMOS process. The line driver drives a 75 Ω resistive load. Its power consumption is 140 mW from a 3.3 V supply. It has a relatively high -3 dB bandwidth (260 MHz) with good phase margin of about 70 degrees. It shows very low THD (-74.5 dB) when drives the load with a 3.3 V peak to peak sine wave at 10 MHz. This architecture reduces the distortion by locating the input differential pair inside the feedback loop and eliminating the distortion of the feedback transistors, which is dominant source of distortion at high frequencies. Thus, it improves the linearity of the output voltage in comparison with previous designs.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.2 pp.416-423
- Publication Date
- 2005/02/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.2.416
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
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Mostafa SAVADI OSKOOEI, Khayrollah HADIDI, Abdollah KHOEI, "A Highly Linear and Large Bandwidth Fully Differential CMOS Line Driver Suitable for High-Speed Data Transmission Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 2, pp. 416-423, February 2005, doi: 10.1093/ietfec/e88-a.2.416.
Abstract: This article describes a large bandwidth and low distortion line driver in a 0.35-µm CMOS process. The line driver drives a 75 Ω resistive load. Its power consumption is 140 mW from a 3.3 V supply. It has a relatively high -3 dB bandwidth (260 MHz) with good phase margin of about 70 degrees. It shows very low THD (-74.5 dB) when drives the load with a 3.3 V peak to peak sine wave at 10 MHz. This architecture reduces the distortion by locating the input differential pair inside the feedback loop and eliminating the distortion of the feedback transistors, which is dominant source of distortion at high frequencies. Thus, it improves the linearity of the output voltage in comparison with previous designs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.2.416/_p
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@ARTICLE{e88-a_2_416,
author={Mostafa SAVADI OSKOOEI, Khayrollah HADIDI, Abdollah KHOEI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Highly Linear and Large Bandwidth Fully Differential CMOS Line Driver Suitable for High-Speed Data Transmission Applications},
year={2005},
volume={E88-A},
number={2},
pages={416-423},
abstract={This article describes a large bandwidth and low distortion line driver in a 0.35-µm CMOS process. The line driver drives a 75 Ω resistive load. Its power consumption is 140 mW from a 3.3 V supply. It has a relatively high -3 dB bandwidth (260 MHz) with good phase margin of about 70 degrees. It shows very low THD (-74.5 dB) when drives the load with a 3.3 V peak to peak sine wave at 10 MHz. This architecture reduces the distortion by locating the input differential pair inside the feedback loop and eliminating the distortion of the feedback transistors, which is dominant source of distortion at high frequencies. Thus, it improves the linearity of the output voltage in comparison with previous designs.},
keywords={},
doi={10.1093/ietfec/e88-a.2.416},
ISSN={},
month={February},}
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TY - JOUR
TI - A Highly Linear and Large Bandwidth Fully Differential CMOS Line Driver Suitable for High-Speed Data Transmission Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 416
EP - 423
AU - Mostafa SAVADI OSKOOEI
AU - Khayrollah HADIDI
AU - Abdollah KHOEI
PY - 2005
DO - 10.1093/ietfec/e88-a.2.416
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2005
AB - This article describes a large bandwidth and low distortion line driver in a 0.35-µm CMOS process. The line driver drives a 75 Ω resistive load. Its power consumption is 140 mW from a 3.3 V supply. It has a relatively high -3 dB bandwidth (260 MHz) with good phase margin of about 70 degrees. It shows very low THD (-74.5 dB) when drives the load with a 3.3 V peak to peak sine wave at 10 MHz. This architecture reduces the distortion by locating the input differential pair inside the feedback loop and eliminating the distortion of the feedback transistors, which is dominant source of distortion at high frequencies. Thus, it improves the linearity of the output voltage in comparison with previous designs.
ER -
English
