IEICE TRANSACTIONS on Fundamentals
Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption
Summary :
In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.12 pp.3044-3051
- Publication Date
- 2009/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.3044
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Device and Circuit Modeling and Analysis
Authors
Keyword
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Mohammad SOLEIMANI, Abdollah KHOEI, Khayrollah HADIDI, Vahid Fagih DINAVARI, "Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3044-3051, December 2009, doi: 10.1587/transfun.E92.A.3044.
Abstract: In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3044/_p
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@ARTICLE{e92-a_12_3044,
author={Mohammad SOLEIMANI, Abdollah KHOEI, Khayrollah HADIDI, Vahid Fagih DINAVARI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption},
year={2009},
volume={E92-A},
number={12},
pages={3044-3051},
abstract={In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.},
keywords={},
doi={10.1587/transfun.E92.A.3044},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3044
EP - 3051
AU - Mohammad SOLEIMANI
AU - Abdollah KHOEI
AU - Khayrollah HADIDI
AU - Vahid Fagih DINAVARI
PY - 2009
DO - 10.1587/transfun.E92.A.3044
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.
ER -
English
