A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations
Summary :
A novel high speed 4-2 compressor using static and pass-transistor logic, has been designed in a 0.35 µm CMOS technology. In order to reduce gate level delay and increase the speed, some changes are performed in truth table of conventional 4-2 compressor which leaded to the simplification of logic function for all parameters. Therefore, power dissipation is decreased. In addition, because of similar paths from all inputs to the outputs, the delays are the same. So there will be no need for extra buffers in low latency paths to equalize the delays.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.4 pp.710-712
- Publication Date
- 2012/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.710
- Type of Manuscript
- BRIEF PAPER
- Category
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Amir FATHI, Sarkis AZIZIAN, Khayrollah HADIDI, Abdollah KHOEI, "A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 4, pp. 710-712, April 2012, doi: 10.1587/transele.E95.C.710.
Abstract: A novel high speed 4-2 compressor using static and pass-transistor logic, has been designed in a 0.35 µm CMOS technology. In order to reduce gate level delay and increase the speed, some changes are performed in truth table of conventional 4-2 compressor which leaded to the simplification of logic function for all parameters. Therefore, power dissipation is decreased. In addition, because of similar paths from all inputs to the outputs, the delays are the same. So there will be no need for extra buffers in low latency paths to equalize the delays.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.710/_p
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@ARTICLE{e95-c_4_710,
author={Amir FATHI, Sarkis AZIZIAN, Khayrollah HADIDI, Abdollah KHOEI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations},
year={2012},
volume={E95-C},
number={4},
pages={710-712},
abstract={A novel high speed 4-2 compressor using static and pass-transistor logic, has been designed in a 0.35 µm CMOS technology. In order to reduce gate level delay and increase the speed, some changes are performed in truth table of conventional 4-2 compressor which leaded to the simplification of logic function for all parameters. Therefore, power dissipation is decreased. In addition, because of similar paths from all inputs to the outputs, the delays are the same. So there will be no need for extra buffers in low latency paths to equalize the delays.},
keywords={},
doi={10.1587/transele.E95.C.710},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations
T2 - IEICE TRANSACTIONS on Electronics
SP - 710
EP - 712
AU - Amir FATHI
AU - Sarkis AZIZIAN
AU - Khayrollah HADIDI
AU - Abdollah KHOEI
PY - 2012
DO - 10.1587/transele.E95.C.710
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2012
AB - A novel high speed 4-2 compressor using static and pass-transistor logic, has been designed in a 0.35 µm CMOS technology. In order to reduce gate level delay and increase the speed, some changes are performed in truth table of conventional 4-2 compressor which leaded to the simplification of logic function for all parameters. Therefore, power dissipation is decreased. In addition, because of similar paths from all inputs to the outputs, the delays are the same. So there will be no need for extra buffers in low latency paths to equalize the delays.
ER -
English
