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IEICE TRANSACTIONS on Fundamentals

Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM

Masaaki IIJIMA, Kayoko SETO, Masahiro NUMA, Akira TADA, Takashi IPPOSHI

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Summary :

Instability of SRAM memory cells derived from aggressive technology scaling has been recently one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. In order to assist the write operation, we address a new memory cell employing a look-ahead body-bias which dynamically controls the threshold voltage. Simulation results have shown improvement in both the write margins and access time without increasing the leakage power derived from the body-bias.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.12 pp.2691-2694
Publication Date
2007/12/01
Publicized
Online ISSN
1745-1337
DOI
10.1093/ietfec/e90-a.12.2691
Type of Manuscript
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category
Memory Design and Test

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