Instability of SRAM memory cells derived from aggressive technology scaling has been recently one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. In order to assist the write operation, we address a new memory cell employing a look-ahead body-bias which dynamically controls the threshold voltage. Simulation results have shown improvement in both the write margins and access time without increasing the leakage power derived from the body-bias.
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Masaaki IIJIMA, Kayoko SETO, Masahiro NUMA, Akira TADA, Takashi IPPOSHI, "Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 12, pp. 2691-2694, December 2007, doi: 10.1093/ietfec/e90-a.12.2691.
Abstract: Instability of SRAM memory cells derived from aggressive technology scaling has been recently one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. In order to assist the write operation, we address a new memory cell employing a look-ahead body-bias which dynamically controls the threshold voltage. Simulation results have shown improvement in both the write margins and access time without increasing the leakage power derived from the body-bias.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.12.2691/_p
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@ARTICLE{e90-a_12_2691,
author={Masaaki IIJIMA, Kayoko SETO, Masahiro NUMA, Akira TADA, Takashi IPPOSHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM},
year={2007},
volume={E90-A},
number={12},
pages={2691-2694},
abstract={Instability of SRAM memory cells derived from aggressive technology scaling has been recently one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. In order to assist the write operation, we address a new memory cell employing a look-ahead body-bias which dynamically controls the threshold voltage. Simulation results have shown improvement in both the write margins and access time without increasing the leakage power derived from the body-bias.},
keywords={},
doi={10.1093/ietfec/e90-a.12.2691},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2691
EP - 2694
AU - Masaaki IIJIMA
AU - Kayoko SETO
AU - Masahiro NUMA
AU - Akira TADA
AU - Takashi IPPOSHI
PY - 2007
DO - 10.1093/ietfec/e90-a.12.2691
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2007
AB - Instability of SRAM memory cells derived from aggressive technology scaling has been recently one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. In order to assist the write operation, we address a new memory cell employing a look-ahead body-bias which dynamically controls the threshold voltage. Simulation results have shown improvement in both the write margins and access time without increasing the leakage power derived from the body-bias.
ER -