Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB
Summary :
A memory controller refreshes DRAM rows periodically in order to prevent DRAM cells from losing data over time. Refreshes consume a large amount of energy, and the problem becomes worse with the future larger DRAM capacity. Previously proposed selective refreshing techniques are either conservative in exploiting the opportunity or expensive in terms of required implementation overhead. In this paper, we propose a novel DRAM selective refresh technique by using page residence in a memory hierarchy of hardware-managed TLB. Our technique maximizes the opportunity to optimize refreshing by activating/deactivating refreshes for DRAM pages when their PTEs are inserted to/evicted from TLB or data caches, while the implementation cost is minimized by slightly extending the existing infrastructure. Our experiment shows that the proposed technique can reduce DRAM refresh power 43.6% on average and EDP 3.5% with small amount of hardware overhead.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E101-C No.3 pp.170-182
- Publication Date
- 2018/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E101.C.170
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Miseon HAN
Korea University
Yeoul NA
Korea University
Dongha JUNG
Korea University
Hokyoon LEE
Korea University
Seon WOOK KIM
Korea University
Youngsun HAN
Kyungil University
Keyword
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Miseon HAN, Yeoul NA, Dongha JUNG, Hokyoon LEE, Seon WOOK KIM, Youngsun HAN, "Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB" in IEICE TRANSACTIONS on Electronics,
vol. E101-C, no. 3, pp. 170-182, March 2018, doi: 10.1587/transele.E101.C.170.
Abstract: A memory controller refreshes DRAM rows periodically in order to prevent DRAM cells from losing data over time. Refreshes consume a large amount of energy, and the problem becomes worse with the future larger DRAM capacity. Previously proposed selective refreshing techniques are either conservative in exploiting the opportunity or expensive in terms of required implementation overhead. In this paper, we propose a novel DRAM selective refresh technique by using page residence in a memory hierarchy of hardware-managed TLB. Our technique maximizes the opportunity to optimize refreshing by activating/deactivating refreshes for DRAM pages when their PTEs are inserted to/evicted from TLB or data caches, while the implementation cost is minimized by slightly extending the existing infrastructure. Our experiment shows that the proposed technique can reduce DRAM refresh power 43.6% on average and EDP 3.5% with small amount of hardware overhead.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E101.C.170/_p
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@ARTICLE{e101-c_3_170,
author={Miseon HAN, Yeoul NA, Dongha JUNG, Hokyoon LEE, Seon WOOK KIM, Youngsun HAN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB},
year={2018},
volume={E101-C},
number={3},
pages={170-182},
abstract={A memory controller refreshes DRAM rows periodically in order to prevent DRAM cells from losing data over time. Refreshes consume a large amount of energy, and the problem becomes worse with the future larger DRAM capacity. Previously proposed selective refreshing techniques are either conservative in exploiting the opportunity or expensive in terms of required implementation overhead. In this paper, we propose a novel DRAM selective refresh technique by using page residence in a memory hierarchy of hardware-managed TLB. Our technique maximizes the opportunity to optimize refreshing by activating/deactivating refreshes for DRAM pages when their PTEs are inserted to/evicted from TLB or data caches, while the implementation cost is minimized by slightly extending the existing infrastructure. Our experiment shows that the proposed technique can reduce DRAM refresh power 43.6% on average and EDP 3.5% with small amount of hardware overhead.},
keywords={},
doi={10.1587/transele.E101.C.170},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB
T2 - IEICE TRANSACTIONS on Electronics
SP - 170
EP - 182
AU - Miseon HAN
AU - Yeoul NA
AU - Dongha JUNG
AU - Hokyoon LEE
AU - Seon WOOK KIM
AU - Youngsun HAN
PY - 2018
DO - 10.1587/transele.E101.C.170
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E101-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2018
AB - A memory controller refreshes DRAM rows periodically in order to prevent DRAM cells from losing data over time. Refreshes consume a large amount of energy, and the problem becomes worse with the future larger DRAM capacity. Previously proposed selective refreshing techniques are either conservative in exploiting the opportunity or expensive in terms of required implementation overhead. In this paper, we propose a novel DRAM selective refresh technique by using page residence in a memory hierarchy of hardware-managed TLB. Our technique maximizes the opportunity to optimize refreshing by activating/deactivating refreshes for DRAM pages when their PTEs are inserted to/evicted from TLB or data caches, while the implementation cost is minimized by slightly extending the existing infrastructure. Our experiment shows that the proposed technique can reduce DRAM refresh power 43.6% on average and EDP 3.5% with small amount of hardware overhead.
ER -
English
