This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.

This paper proposes an LDMOSFET (Lateral Double-diffused MOSFET) that has the robustness against the hardest ESD (Electrostatic Discharge) requirement for automobile ECUs (Electronic Control Units) of discharging 25 kV 150 pF through 150 ohm 1 µH without external protecting circuits. The basic idea to achieve this is to add a novel discharge circuit to an LDMOSFET, which turns on when Human Body Model (HBM) type ESD is applied, and to consume the discharge energy in SOA (Safe Operating Area) in the LDMOSFET, avoiding localized current crowding of a parasitic bipolar transistor which causes the conventional ESD device failure. First, dynamics of current crowding when a grounded gate LDMOSFET is exposed to ESD stress is described by means of a circuit level SPICE simulation on a parallel distributed device model. Then a novel ESD turn-on LDMOSFET with a discharge MOSFET is proposed, which has ESD robustness of 25 kV. Finally the ESD measurements of the new device are shown to be in good accordance with estimation and to satisfy the target.

The variabilities of device characteristics are usually regarded as a normal distribution. If we consider the variabilities over the whole wafer, however, they cannot be expressed as a normal distribution due to the existence of global systematic component. We propose a statistical model, characterizing the global systematic component according to the distance from the center of the wafer, which can express the variabilities over the whole wafer statistically.

In current-mode signal processing, a companding integrator is attractive from the viewpoint of linearity under a low power supply voltage. In this paper, new instantaneous companding integrators using MOSFET's are proposed. The companding integrator utilizes a nature of MOSFET square law. HSPICE simulation results demonstrate several advantages of the proposed circuits.

A comprehensive analysis methodology allowing investigation of the RF performance of Si and strained Si:SiGe MOSFETs is presented. It is based on transient ensemble Monte Carlo simulation which correctly describes device transport, and employs a finite element solver to account for complex device geometries. Transfer characteristics and figures of merit for a number of existing and proposed RF MOSFETs are discussed.

The gate oxide of sub-0.1 µm MOSFETs channel length is expected to be reduced beyond 3 nm in spite of an increasing direct tunneling gate current. As tunnel injection modeling into SiO2 is expected to depend on the electron transport model adopted for the device description, a critical comparison is made in this paper between gate currents obtained from simulators based on Drift-Diffusion, Energy-Balance, and Monte Carlo models. The studied device is a 0.07 µm channel length n-MOSFET with 1.5 nm thick gate oxide. It is shown that positive drain voltage is responsible for two opposite effects on DT leakage: a carrier heating and a potential barrier hardening along the channel. It is proved by a careful study of Monte Carlo microscopic quantities that, contrary to what holds for thicker gate oxide transistors, the balance is favorable to the potential barrier effect. Injection into SiO2 is then dominated by near-thermal carriers injected at the channel beginning. For this reason, the gate current decreases when increasing the drain bias, with the maximum leakage obtained for (Vgs=Vdd, Vds=0), and a correct agreement is obtained between the Drift-Diffusion, Energy-Balance, and Monte Carlo approaches of gate current calculation, in spite of very different physical descriptions of transport at the microscopic level.

We have studied the characteristic trade-offs in low power and low voltage MOSFETs from the viewpoint of back-gate control and body effect factor. Previously reported MOSFET structures are classified into four categories in terms of back-gate structures. It is shown that a MOSFET with a fixed back-bias has only a limited current drive at low voltage irrespective of device structures, while current drive of a dynamic threshold MOSFET with body tied to gate is more enhanced with increasing body effect factor. We have proposed a new dynamic threshold MOSFET, electrically induced body (EIB) DTMOS, which has a very large body effect factor at low threshold voltage and high current drive at low supply voltage.

There is increasing interest using CMOS circuits for highly integrated high frequency wireless telecommunications systems. This paper reviews recent works in transceiver architectures, circuits and devices technology for CMOS RFIC application. A number of practical problems those must be resolved in CMOS RFIC design are also discussed.

This paper reports the evaluation results of the channel boron distribution in the deep sub-0.1 [µm] n-MOSFETs for the first time. It has been found that the boron depletion effect becomes dominant and the reverse short channel effect becomes less significant in the deep sub-0.1 [µm] n-MOSFETs. It has been also found that the sheet charge distribution responsible for the reverse short channel effect is localized within a distance of 100 [nm] from the source/drain-extension junction.

Electro-thermal characteristics of the Si MOSFET in transient state are reported using a non-isothermal device simulator where both the transistor's self-heating and the thermal influence of its neighboring devices are duly taken into account. The thermal influence is estimated using a three-dimensional thermal simulator. Based on this set-up, we predict time-dependent electro-thermal characteristics of the Si MOSFET at gate switching and its drain breakdown conditions. We show that the time delay between the electrical response and the lattice temperature rise, is significant and thus can not be neglected. In addition, we found that avalanche and thermal breakdown characteristics largely depend on the slope of the drain input voltage.

The full-band Monte Carlo technique is currently the most accurate device simulation method, but its usefulness is limited because it is very CPU intensive. This work describes efficient algorithms in detail, which raise the efficiency of the full-band Monte Carlo method to a level where it becomes applicable in the device design process beyond exemplary simulations. The k-space is discretized with a nonuniform tetrahedral grid, which minimizes the discretization error of the linear energy interpolation and memory requirements. A consistent discretization of the inverse mass tensor is utilized to formulate efficient transport parameter estimators. Particle scattering is modeled in such a way that a very fast rejection technique can be used for the generation of the final state eliminating the main cause of the inefficiency of full-band Monte Carlo simulations. The developed full-band Monte Carlo simulator is highly efficient. For example, in conjunction with the nonself-consistent simulation technique CPU times of a few CPU minutes per bias point are achieved for substrate current calculations. Self-consistent calculations of the drain current of a 60nm-NMOSFET take about a few CPU hours demonstrating the feasibility of full-band Monte Carlo simulations.

During past decade MOS transistors have been aggressively scaled to dimensions below sub-quarter micron, the so called ultra deep submicron (UDSM) technology. At these dimensions transistor characteristics can not be accurately modeled using classical approach presently used in the most commonly used MOSFET models such as BSIM3, MOS9 etc, without recourse to large number of empirical parameters. In this paper we will discuss short comings of the present models and show how to overcome them using a hybrid approach of modeling, wherein both function regional and surface potential based approaches are combined together, that results in a model that reflects UDSM device behavior with smaller set of physically meaningful, and easily extractable model parameters. Various physical effects that need to be considered for UDSM modeling such as quantization of the inversion layer carrier, mobility degradation, carrier velocity saturation and overshoot, polydepletion effect, bias dependent source/drain resistance, vertical and lateral doping profiles, etc. will be discussed.

Fluctuations of three device parameters (Tox, Nsub, ΔL) based on process fluctuations are taken as cause of device/circuit performances. In-line measured device parameters are approximated by Gaussian functions, and their 2σ values are assigned as boundaries of the performance fluctuations. Measured distributions both for device and curcuit performances are successfully reproduced.

We propose a new inverse modeling method to extract 2D channel dopant profile in an MOSFET. The profile is extracted from threshold voltage (Vth) of MOSFETs with a series of gate lengths. The uniqueness of the extracted channel and drain profile is confirmed through test simulations. The extracted profile of actual 0.1 µm nMOSFETs explains reverse short channel effects (RSCE) of threshold voltage dependent on gate length including substrate bias dependence.

Profiles of photoemission induced by hot electrons in LDD-type n-MOSFETs with L = 0.35-2.0 µm were measured with a photoemission microscope, which had a capability of 1000 magnification and a spatial resolution of 27 nm/pixel on a CCD imager sufficient to detect profile changes in the channel length direction. Under the bias condition of maximum substrate current, photoemission peaks were located at the LDD-drain edge and the n+-drain edge for the devices with L = 0.35 and L 0.40 µm, respectively. A peak position, only in the case of the 0.35 µm device, shifted toward the drain side by about 80 nm at VD = 7.0 V. Since VD did not affect peak positions in L 0.40 µm devices, the photoemission mechanisms may be different between L = 0.35 µm and L 0.40 µm devices. The photoemission points due to p-n junction breakdown were located at the cylindrical curvature edge of the n+-drain region. Two-dimensional device simulation, even when the lateral electric field, electron temperature and radiative recombination rate were taken into account, could not explain the experimental results completely.

MOSFETs with sub-0.1 µm gate length were fabricated, and their low temperature operation was investigated. The drain current for drain voltage of 2 V increased monotonously as temperature was lowered to 15 K without an influence of the freeze-out effect. Moreover, the increase in the drain current was enhanced by the gate length reduction. The hot-carrier effect at low temperature was also investigated. Impact-ionization decreased as temperature was lowered under the condition of drain voltage 2 V. The decreasing ratio was enhanced as gate length became shorter. We consider this phenomenon is attributed to the non-steady-stationary effect. As a result, device degradation by DC stressing was reduced at 77 K in comparison with room temperature. In the case of 0.1 µm MOSFET, drain current was not degraded in condition of DC stress with gate- and drain-voltage was 1.5 V.

A non-isothermal device simulation, consisting of solving heat flow equation three-dimensionally together with other semiconductor equations two-dimensionally, is reported for various arrangements of a pluralty of transistors mounted on a single chip. These arrangements are intended to simulate the real situation in an IC chip whereas a three-dimensional solution of the heat flow equation is aimed at accurately determining the thermal interdependence among individual transistors. As a result, the drain current versus drain voltage characteristics of a miniaturized transistor is found to exhibit a heat-induced negative resistance region.

Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2µm fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a nonuniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.

This paper describes novel techniques for analyzing power MOSFETs. Since the gate width of power MOSFETs is much larger than that of power MESFETs or HJFETs, an appropriate device design to suppress matching circuit losses is needed. These losses and the intrinsic device characteristics are analyzed employing the proposed techniques, which are based on large-signal simulations. Also, new formulas describing the dependence of saturated output power on gate width are derived to perform loss-minimized design. These techniques are applied to the design of power MOSFETs for GSM cellular telephones. As a result, an output power of 35.5 dBm with a power-added efficiency of 55% and a power gain of 10.5 dB at 900 MHz have been achieved.

We have been studying on subthreshold characteristics of SOI (Silicon-On-Insulator) MOSFET's in terms of substrate bias dependence using a one-dimensional subthreshold device simulator based on Poisson equation in an SOI multilayer structure for estimating structural parameters of real devices. Here, we consider the quantum mechanical effects in the electron inversion layer of thin SOI MOSFET's, such as the two-dimensionally quantized electron states and transports, with a self-consistent solver of Poisson and Schrodinger equations and a mobility model by the relaxation time approximation. From results of simulations, we found a significant difference between this model and the classical model and concluded that the quantum mechanical effects need to be considered in analizing thin-film SOI devices.