An equivalent MOSFET circuit with a wide input range is proposed. The proposed circuit is suitable for a realization of a wide input range under a low power supply voltage. The circuit consists of a MOSFET array and level shift circuits. The sum of drain currents of the MOSFET array is used as an equivalent drain current. The equivalent drain current is represented by K(VGS-VT)2 even when its drain-to-source voltage is quite small and some MOSFETs in the array are in the non-saturation region or the cut-off region. The input range of the proposed circuit realized by k-MOSFET array is k times as wide as that of a single MOSFET. It is confirmed through HSPICE simulations that the proposed circuit is effective in applications with a wide dynamic range.

This paper proposes a method for constructing an interface between an operations system and a workstation (OpS-WS interface) in a telecommunications management system based on TMN. To construct this interface, an appropriate communication protocol must be selected to perform management through efficient message exchange. The human machine interface provided by the WS should specify the managed objects. The interface also needs to be implemented so as to minimize the software revisions needed when the computer or its associated window system, or both, are changed. The proposed method addresses all these requirements. GUI components for realizing the HMI function are defined as Managed Objects as are communication network resources. Therefore, the communication protocol in TMN is defined as unique and it is possible to separate the HMI Interface from the OpS. CMIP is employed as the communication protocol to provide efficient message exchange. Software components that realize the human machine interface are selected so as to satisfy functional requirements specific to telecommunications management. The managed objects (MOs) and their relationships are investigated in order to represent these components appropriately. In the proposed method, the CMIP-based OpS-WS interface allows the OpS to take the manager role and the WS take the agent role. An implementation technique for MOs is also presented. The technique enables the software that implements MO behaviour to be coded easily. A prototype is built to confirm the correct operation of the proposed OpS-WS interface, and it is shown that CMIP requires fewer message exchanges to indicate alarms on the WS than other protocols. The proposed method is also advantageous because of its flexibility. That is, the WS software can be updated with little effort when the computer or its associated window system, or both, are changed.

This paper proposes a new charge pump to suppress spurious noise of phase-locked loops. The spurious noise is induced by charge injection generated from the parasitic capacitors associated with switches and the current-mismatch between the charging and discharging currents of the charge pump. A new charge pump is configured by adding an operational amplifier, a sample-and-hold circuit, and switches to a basic charge pump. During the idling time of the charge pump, the currents of the current sources are adjusted and the current-mismatch are reduced to 0.3%. Applying the proposed charge pump to a phase-locked loop, we can suppress the spurious noise by 18 dB compared with a PLL using a basic one.

In the correspondence discrete Wigner higher order spectra (WHOS) of harmonizable random signals are addressed and their relations with polyspectra (HOS) are illustrated. It is shown, that discrete WHOS of a random stationary signal do not reduce to the aliased polyspectra in a similar way as Wigner distribution (WD) reduces to the power spectrum of a random signal. Wigner 2nd-order time-frequency distribution of deterministic signals and the 3rd-order spectrum of stationary signals are presented in their modified forms to be used to estimate time-varying third-order spectrum of discrete nonstationary random harmonizable processes.

This paper discusses a new design method for 2-D variable FIR digital filters, which is an extension of our previous work for 1-D case. The method uses a 3-D prototype FIR filter whose cross-sections correspond to the desired characteristics of 2-D variable FIR filters. A 2-D variable-angle FIR fan filter is given as a design example.

A multi-path structure is proposed for reduction in effect of digital substrate noise which degrades analog circuit performance. As an example low-pass filters are implemented in a 0.18-µm CMOS process. 11-dBm reduction in digital substrate noise is achieved as compared with a conventional structure.

This paper proposes a novel method to realize highly linear MOS circuits using MOSFETs in the nonsaturation region. The proposed method is based on the cancellation of nonlinearity of two MOSFETs by using a current inversiontype negative impedance converter. First, grounded and floating resistor realizations are discussed. Next, by exploiting the MOS resistor circuits, gyrators and inductors are realized. As an application example, a third-order doubly-terminated LC filter is simulated. SPICE analysis shows low total harmonic distortions, excellent controllability and small gain error in the passband.

This paper presents a 7th-order channel-select filter for a spread-spectrum wireless receiver operating with a minimum power supply of 2.5 V. The channel-select filter implements a sharp transition from 2 MHz to 4 MHz and a stopband attenuation of 50 dB. The 7th-order filter is realized by a cascade of a passive RC integrator, a 3rd-order leapfrog filter, an operational amplifier based differentiator, a 2nd-order notch filter, and a 1st-order allpass filter. It is designed in a 0.35 µm single-poly BiCMOS process. Simulation results show feasibility of the proposed filter.

A high-speed transconductance-C-opamp integrator using a current-feedback amplifier is proposed. The integrator has good frequency response compared with a conventional transconductance-C-opamp integrator using a voltage-feedback amplifier. The current-feedback amplifier shifts the second pole of the proposed integrator to the upper frequency. The frequency is proportional to the current gain of the current-feedback amplifier. The proposed integrator can eliminate effects of the parasitics at the output node of the transconductance since the voltage at the node is fixed. One of the circuit examples of the proposed integrator is shown. Its validity is confirmed through HSPICE simulations. The proposed integrator works as predicted up to 260 MHz.

This paper proposes a fully balanced circuit structure with a zero common-mode gain. The common-mode gain of the proposed structure becomes theoretically zero with a perfect device matching. Even if a perfect device matching is not achieved, the common-mode signal can be sufficiently suppressed by the feedback loops provided with the structure. Based on this concept, an integrator is composed. Furthermore the concept can be directly applied to a filter design. The application results in reduced chip area. A design example of a second-order filter and simulation results verify the theoretical expectation.

In practical applications of digital filters it is more realistic to treat multiplier coefficients as finite intervals than restricting them to infinite or very long word-length representations. However, this can not be done it the frequency response performance under interval assumption is difficult to analyze. In this paper, it is proved that stable lattice allpass filters possess bounded continuous phase response when lattice parameters vary in bounded intervals. It is shown that sharp bounds on the interval phase response can be computed easily at an arbitrary frequency using a simple recursive procedure. Application of this property to the problem of finite word-length lattice allpass filter design is also discussed. By formulating this problem as an interval design it is possible to solve it efficiently independent of the number system used to represent multiplier coefficients.

Voltage follower is one of the most useful building blocks in analog circuits. This paper proposes a voltage follower composed of a complementary pair of p-channel MOS(PMOS) and n-channel MOS (NMOS) differential amplifiers which operates under low power supply. The proposed circuit has a rail-to-rail dynamic range by combining complementary differential amplifiers.

In multidimensional signal sampling, the orthogonal sampling scheme is the simplest one and is employed in various applications, while a non-orthogonal sampling scheme is its alternative candidate. The latter sampling scheme is used mainly in application where the reduction of the sampling rate is important. In three-dimensional (3-D) signal processing, there are two typical sampling schemes which belong to the non-orthogonal samplings; one is face-centered cubic sampling (FCCS) and the other is body-centered cubic sampling (BCCS). This paper proposes a new design method for 3-D band-limiting FIR filters required for such non-orthogonal sampling schemes. The proposed method employs the McClellan transformation technique. Unlike the usual 3-D McClellan transformation, however, the proposed design method uses 2-D prototype filters and 2-D transformation filters to obtain 3-D FIR filters. First, 3-D general sampling theory is discussed and the two types of typical non-orthogonal sampling schemes, FCCS and BCCS, are explained. Then, the proposed design method of 3-D bandlimiting filters for these sampling schemes is explained and an effective implementation of the designed filters is discussed briefly. Finally, design examples are given and the proposed method is compared with other method to show the effectiveness of our methos.

This paper proposes a rail-to-rail OTA. By adding a signal decomposing circuit at the input of given OTAs that have a limited input voltage range, a rail-to-rail OTA is obtained. Each decomposed input voltage signal is converted to a current signal by an OTA and each output current of OTAs is summed to obtain a linear output signal. Since the input signal is decomposed into small magnitude voltage signals, the OTAs used to the voltage-current conversion do not require a wide input-range and any OTA can be used to realize a rail-to-rail input voltage range OTA. HSPICE simulations are performed to verify the validity of the proposed method.

This paper proposes a jitter tolerant continuous-time sigma-delta A-D converter structure as well as its design method. This method transforms a conventionally designed sigma-delta A-D converter into a jitter tolerant one. Jitter tolerance is provided by the modified feedback signal paths and a consequently inserted digital LPF. This method is applicable independently of a system order and the other specifications.

This paper proposes a design technique for 3-D non-separable QMF banks with Face-Centered Cubic Sampling (FCCS) and Body-Centered Cubic Sampling (BCCS). In the proposed technique, 2-D McClellan transformation is applied to a suitably designed 2-D prototype QMF to obtain 3-D QMFs. The design examples given in this paper demonstrate advantages of the proposed method.

It is shown that two-dimensional linear phase FIR digital filters with various shapes of frequency response can be designed and realized as modular array structures free of multiplier coefficients. The design can be performed by judicious selection of two low order linear phase transfer functions to be used at each module as kernel filters. Regular interconnection of the modules in L rows and K columns conditioned with boundary coefficients 1, 0 and 1/2 results in higher order digital filters. The kernels should be chosen appropriately to, first, generate the desired shape of frequency response characteristic and, second, lend themselves to multiplierless realization. When these two requirements are satisfied, the frequency response can be refined to possess narrower transition bands by adding additional rows and columns. General properties of the frequency response of the array are investigated resulting in Theorems that serve as valuable tools towards appropriate selection of the kernels. Several design examples are given. The array structures enjoy several favorable features. Specifically, regularity and lack of multiplier coefficients makes it suitable for high-speed systolic VLSI implementation. Computational complexity of the structure is also studied.

This paper presents an automatic synthesis method of active analog circuits that uses evolutionary search and employs some topological features of analog integrated circuits. Our system firstly generates a set of circuits at random, and then evolves their topologies and device sizing to fit an environment which is formed by the fitness function translated from the electrical specifications of the circuit. Therefore expert knowledge about circuit topologies and sizing are not needed. The capability of this method is demonstrated through experiments of automatic synthesis of CMOS operational amplifiers.

In this paper, a new design idea for class A CMOS second generation current conveyor (CCII) is discussed. Based on the proposed idea, a new architecture for a CMOS CCII is presented. The proposed circuit is free from body effect and provides high performance in terms of input resistance and transfer gain errors. HSPICE simulation results also have shown remarkable performance over the wide bandwidth.

FIR digital filters composed of parallel multiple subfilters are proposed. A binary expression of an input signal is decomposed into multiple shorter words, which drive the subfilters having different length. The output error is evaluated by mean squared and maximum spectra. A fast algorithm is also proposed to determine optimal filter lengths and coefficients of subfilters. Many examples confirm that the proposed filters generate smaller output errors than conventional filters under the condition of specified number of multiplications and additions in filter operations. Further, multiplier and adder structures (MAS) to perform the operations of the proposed filters are also presented. The number of gates used in the proposed MAS and its critical path are estimated. The effectiveness of the proposed MAS is confirmed.