Automatic design of analog circuits using a programmed algorithm is in great demand because optimal analog circuit design in a short time is required due to the limited development time. Although an automatic design using equation-based method can design simple circuits fast and accurately, it cannot solve complex circuits. On the other hand, an automatic design using optimization algorithm such as Ant Colony Optimization, Genetic Algorithm, and so on, can design complex circuits. However, because these algorithms are based on the stochastic optimization technique and determine the circuit parameters at random, a lot of circuits which do not operate in principle are generated and simulated to find the circuit which meets specifications. In this paper, to reduce the search space and the redundant simulations, automatic design using both equation-based method and a genetic algorithm is proposed. The proposed method optimizes the bias circuit blocks using the equation-based method and signal processing blocks using Genetic Algorithm. Simulation results indicate that the evaluation value which considers the trade-off of the circuit specification is larger than the conventional method and the proposed method can design 1.4 times more circuits which satisfy the minimum requirements than the conventional method.

This paper proposes a rail-to-rail OTA. By adding a signal decomposing circuit at the input of given OTAs that have a limited input voltage range, a rail-to-rail OTA is obtained. Each decomposed input voltage signal is converted to a current signal by an OTA and each output current of OTAs is summed to obtain a linear output signal. Since the input signal is decomposed into small magnitude voltage signals, the OTAs used to the voltage-current conversion do not require a wide input-range and any OTA can be used to realize a rail-to-rail input voltage range OTA. HSPICE simulations are performed to verify the validity of the proposed method.

This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC conversion steps than a binary search algorithm, but we show that the sampling speed of an SAR ADC using this algorithm can be faster than that of a conventional binary-search SAR ADC -- because the latter must wait for the settling time of the DAC inside the SAR ADC.

As current-voltage characteristics of GaAs MESFET differ from those of BJT and MOSFET and n-channel FET is only practically in use, the development of GaAs MESFET analog integrated circuits is left behind. In this paper, two circuit techniques to improve the performance of GaAs MESFET analog circuits are provided. The one is to realize a high impedance active load circuit which dose not need CMFB (Common Mode Feed Back) to achieve stable DC biasing point. The other is to cancel the harmonic destortion caused by nonlinear characteristics of GaAs MESFETs. As an application example of the proposed circuits, biquad low-pass and band-pass filters are realized and simulated by HSPICE to verify the validity of the proposed method.

In this paper, current-mode integrators which consist of only n-channel depletion-mode FET and their application to filters are presented. Lossy integrator is simply realized with a capacitor and a grounded gate FET. Lossless integrator can be obtained by providing a lossy integrator with a positive feedback. To do this, multi-output current mirror is proposed. To reduce 2nd-order harmonic and THD of the filter, unbalanced/balanced conversion circuit is proposed. As an application example, 3rd-order leapfrog low-pass Chebyshev filter is simulated with GaAs MESFET process parameters. Simulation results show good performances.

This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.

Sawtooth wave generator which has very steep down-slope and little amplitude and oscillation frequency error, is proposed. Because the down-slope is achieved by switching two triangular waves exclusively, the shape of the down-slope becomes very steep. The proposed method realizes not only the steep down-slope but also less amplitude error and less oscillation frequency error compared with conventional method. Spectre simulations are performed by using 0.18 µm CMOS process and transient simulation results show the proposed circuit has quite less amplitude and frequency error for 5 MHz oscillation compared with the conventional method.

In current-mode signal processing, a companding integrator is attractive from the viewpoint of linearity under a low power supply voltage. In this paper, new instantaneous companding integrators using MOSFET's are proposed. The companding integrator utilizes a nature of MOSFET square law. HSPICE simulation results demonstrate several advantages of the proposed circuits.

In this paper, rail-to-rail OTA utilizing linear V-I conversion circuit whose input stage is composed of single channel MOSFETs, is proposed. The proposed conversion circuit is realized with two circuit blocks. One of them consists of a single MOSFET operating in plural regions and the other a pair of MOSFETs in saturation region and cut-off region. Combination of the circuit blocks achieves a linear voltage-current conversion for a rail-to-rail input signal. Rail-to-rail OTA is proposed using the proposed conversion circuit. HSPICE simulations are performed to verify the validity of the proposed V-I converter and rail-to-rail OTA. Simulation results indicate good performances. As an application example, 2nd-order LPF is realized using the proposed OTAs.

This paper proposes spread-spectrum clock modulation algorithms for EMI reduction in digitally-controlled DC-DC converters. In switching regulators using PWM, switching noise and harmonic noise concentrated in a narrow spectrum around the switching frequency can cause severe EMI. Spread-spectrum clock modulation can be used to minimize EMI. In conventional switching regulators using analog control it is very difficult to realize complex spread-spectrum clocking, however this paper shows that it is relatively easy to implement spread-spectrum EMI-reduction using digital control. The proposed algorithm was verified using a power converter simulator (SCAT).