This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.

This paper describes a high-speed, robust, scalable, and low-cost feed-forward time amplifier that uses phase detectors and variable delay lines. The amplifier works by detecting the time difference between two rising input edges with a phase detector and adjusting the delay of the variable delay line accordingly. A test chip was designed and fabricated in 65 nm CMOS. The measured resulting performance indicates that it is possible to amplify time difference while maintaining high-speed operation.

This paper proposes a new flash time-to-digital converter (TDC) circuit which exploits unbalanced arbiters to integrate intrinsic delay offsets into the decision elements. The unbalanced arbiters are implemented with cross-coupled standard NAND cells and the combination of the NAND cells decides the timing offset between two input signals. Simulations and measurements are conducted to validate the new circuit, which provides variable time difference ranges by controlling the slope of input signals. Since the proposed flash TDC uses only NAND cells in a standard cell library for the arbiters which easily enables the TDC to be used as a soft macro in a typical digital circuit design flow.