IEICE TRANSACTIONS on Fundamentals
A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters
Summary :
This paper proposes a new flash time-to-digital converter (TDC) circuit which exploits unbalanced arbiters to integrate intrinsic delay offsets into the decision elements. The unbalanced arbiters are implemented with cross-coupled standard NAND cells and the combination of the NAND cells decides the timing offset between two input signals. Simulations and measurements are conducted to validate the new circuit, which provides variable time difference ranges by controlling the slope of input signals. Since the proposed flash TDC uses only NAND cells in a standard cell library for the arbiters which easily enables the TDC to be used as a soft macro in a typical digital circuit design flow.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.3 pp.777-780
- Publication Date
- 2014/03/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E97.A.777
- Type of Manuscript
- Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
Satoshi KOMATSU
The University of Tokyo
Takahiro J. YAMAGUCHI
ADVANTEST Laboratories Ltd.
Mohamed ABBAS
The University of Tokyo
Nguyen Ngoc MAI KHANH
The University of Tokyo
James TANDON
The University of Tokyo
Kunihiro ASADA
The University of Tokyo
Keyword
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Satoshi KOMATSU, Takahiro J. YAMAGUCHI, Mohamed ABBAS, Nguyen Ngoc MAI KHANH, James TANDON, Kunihiro ASADA, "A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters" in IEICE TRANSACTIONS on Fundamentals,
vol. E97-A, no. 3, pp. 777-780, March 2014, doi: 10.1587/transfun.E97.A.777.
Abstract: This paper proposes a new flash time-to-digital converter (TDC) circuit which exploits unbalanced arbiters to integrate intrinsic delay offsets into the decision elements. The unbalanced arbiters are implemented with cross-coupled standard NAND cells and the combination of the NAND cells decides the timing offset between two input signals. Simulations and measurements are conducted to validate the new circuit, which provides variable time difference ranges by controlling the slope of input signals. Since the proposed flash TDC uses only NAND cells in a standard cell library for the arbiters which easily enables the TDC to be used as a soft macro in a typical digital circuit design flow.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.777/_p
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@ARTICLE{e97-a_3_777,
author={Satoshi KOMATSU, Takahiro J. YAMAGUCHI, Mohamed ABBAS, Nguyen Ngoc MAI KHANH, James TANDON, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters},
year={2014},
volume={E97-A},
number={3},
pages={777-780},
abstract={This paper proposes a new flash time-to-digital converter (TDC) circuit which exploits unbalanced arbiters to integrate intrinsic delay offsets into the decision elements. The unbalanced arbiters are implemented with cross-coupled standard NAND cells and the combination of the NAND cells decides the timing offset between two input signals. Simulations and measurements are conducted to validate the new circuit, which provides variable time difference ranges by controlling the slope of input signals. Since the proposed flash TDC uses only NAND cells in a standard cell library for the arbiters which easily enables the TDC to be used as a soft macro in a typical digital circuit design flow.},
keywords={},
doi={10.1587/transfun.E97.A.777},
ISSN={1745-1337},
month={March},}
Copy
TY - JOUR
TI - A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 777
EP - 780
AU - Satoshi KOMATSU
AU - Takahiro J. YAMAGUCHI
AU - Mohamed ABBAS
AU - Nguyen Ngoc MAI KHANH
AU - James TANDON
AU - Kunihiro ASADA
PY - 2014
DO - 10.1587/transfun.E97.A.777
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2014
AB - This paper proposes a new flash time-to-digital converter (TDC) circuit which exploits unbalanced arbiters to integrate intrinsic delay offsets into the decision elements. The unbalanced arbiters are implemented with cross-coupled standard NAND cells and the combination of the NAND cells decides the timing offset between two input signals. Simulations and measurements are conducted to validate the new circuit, which provides variable time difference ranges by controlling the slope of input signals. Since the proposed flash TDC uses only NAND cells in a standard cell library for the arbiters which easily enables the TDC to be used as a soft macro in a typical digital circuit design flow.
ER -
English
