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[Author] Nguyen Ngoc MAI KHANH(4hit)

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  • A 0.18-µm CMOS X-Band Shock Wave Generator with an On-Chip Dipole Antenna and a Digitally Programmable Delay Circuit for Pulse Beam-Formability

    Nguyen Ngoc MAI KHANH  Masahiro SASAKI  Kunihiro ASADA  

     
    PAPER

      Vol:
    E94-C No:4
      Page(s):
    627-634

    In this paper, we present a 0.18-µm CMOS fully integrated X-band shock wave generator (SWG) with an on-chip dipole antenna and a digitally programmable delay circuit (DPDC) for pulse beam-formability in short-range and hand-held microwave active imaging applications. This chip includes a SWG, a 5-bit DPDC and an on-chip wide-band meandering dipole antenna. By using an integrated transformer, output pulse of the SWG is sent to the on-chip meandering dipole antenna. The SWG operates based on damping conditions to produce a 0.4-V peak-to-peak (p-p) pulse amplitude at the antenna input terminals in HSPICE simulation. The DPDC is designed to adjust delays of shock-wave outputs for the purpose of steering beams in antenna array systems. The wide-band dipole antenna element designed in the meandering shape is located in the top metal of a 5-metal-layer 0.18-µm CMOS chip. By simulating in Momentum of ADS 2009, the minimum value of antenna's return loss, S 11, and antenna's bandwidth (BW) are -19.37 dB and 25.3 GHz, respectively. The measured return loss of a stand-alone integrated meandering dipole is from -26 dB to -10 dB with frequency range of 7.5-12 GHz. In measurements of the SWG with the integrated antenna, by using a 20-dB standard gain horn antenna placed at a 38-mm distance from the chip's surface, a 1.1-mVp-p shock wave with a 9-11-GHz frequency response is received. A measured 3-ps pulse delay resolution is also obtained. These results prove that our proposed circuit is suitable for the purpose of fully integrated pulse beam-forming system.

  • A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application

    Nguyen Ngoc MAI KHANH  Masahiro SASAKI  Kunihiro ASADA  

     
    PAPER-Device and Circuit Modeling and Analysis

      Vol:
    E94-A No:12
      Page(s):
    2554-2562

    This paper presents a 65-nm CMOS 8-antenna array transmitter operating in 117–130-GHz range for short range and portable millimeter-wave (mm-wave) active imaging applications. Each antenna element is a new on-chip antenna located on the top metal. By using on-chip transformer, pulse output of each resistor-less mm-wave pulse generators (PG) are sent to each integrated antenna. To adjust pulse delays for the purpose of pulse beam-forming, a 7-bit digitally programmable delay circuit (DPDC) is added to each of PGs. Moreover, in order to dynamically adjust pulse delays among eight SW's outputs, we implemented on-chip jitter and relative skew measuring circuit with 20-bit digital output to achieve cumulative distribution (CDF) and probability density (PDF) functions from which DPDC's input codes are decided to align eight antenna's output pulses. Two measured radiation peaks after relative skew alignment are obtained at (θ; φ) angles of (-56; 0) and (+57; 0). Measurement results shows that beam-forming angles of the fully integrated antenna array can be adjusted by digital input codes and by the on-chip skew adjustment circuit for active imaging applications.

  • A 0.25-µm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging

    Nguyen Ngoc MAI KHANH  Masahiro SASAKI  Kunihiro ASADA  

     
    PAPER-Microwave and Millimeter-Wave Antennas

      Vol:
    E94-C No:10
      Page(s):
    1626-1633

    This paper presents a 100–120-GHz pulse transmitter chip with a 5424 on-chip loop antenna array for the purpose of beam-formability in portable millimeter-wave (mm-wave) active imaging applications. We present a new idea for silicon-based mm-wave pulse beam-forming by using voltage-varied CMOS inverter chain. This 4-mm4-mm transmitter chip is designed and fabricated in a 2.5-V 0.25-µm 4-metal-layer Si-Ge Bi-CMOS process. The 30-µm30-µm loop antenna located on the top-metal layer operates as an coil in an integrated mm-wave pulse generator. Each of on-chip pulse generators employing under-damped/over-damped conditions to produce mm-wave pulses includes an R-L-C circuit, a bipolar junction transistor (BJT) operated as a switch and a CMOS inverter chain circuit for shaping the rising edge of the input clock. Simulation results by ADS 2009 and HSPICE show that loop antenna' inductance and resistance at 80–120-GHz are 51 pH and 3 Ω, respectively. A simulation performance of an integrated 136 loop antenna array illustrates the variation of maximum radiation angles depending on different phase values between array's elements. By using an mm-wave power meter, a 90–140-GHz standard horn antenna and a Schottky diode detector, several measured radiation patterns of this loop antenna array chip are achieved. From the measurement result, we demonstrate the possibility of an integrated mm-wave pulse generator for the purpose of beam-forming by changing power supplies of inverter chains.

  • A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters

    Satoshi KOMATSU  Takahiro J. YAMAGUCHI  Mohamed ABBAS  Nguyen Ngoc MAI KHANH  James TANDON  Kunihiro ASADA  

     
    LETTER

      Vol:
    E97-A No:3
      Page(s):
    777-780

    This paper proposes a new flash time-to-digital converter (TDC) circuit which exploits unbalanced arbiters to integrate intrinsic delay offsets into the decision elements. The unbalanced arbiters are implemented with cross-coupled standard NAND cells and the combination of the NAND cells decides the timing offset between two input signals. Simulations and measurements are conducted to validate the new circuit, which provides variable time difference ranges by controlling the slope of input signals. Since the proposed flash TDC uses only NAND cells in a standard cell library for the arbiters which easily enables the TDC to be used as a soft macro in a typical digital circuit design flow.