In this paper we present an on-chip noise detection circuit. In contrast with the previous works concerning on-chip noise measurement, this detector does not assume specific noise properties such as periodicity. The detector is able to continuously capture 10 nano-second time window from the measured signal with a resolution equal to 100 pico-second. The requested bandwidth of the output channel can be adjusted freely, therefore, the user can avoid the effect of on-chip parasites and the need to off-chip sophisticated monitoring tools. The detector is equipped with an on-chip programmable voltage divider, which enables measuring the high and low swing fluctuations accurately. Therefore, the detector is suitable to measure the non-periodic/single event noise for the purpose of reliability evaluation and performance modeling. The detector is implemented in a test chip using Hitachi 0.18 µm technology.

This paper proposes a new flash time-to-digital converter (TDC) circuit which exploits unbalanced arbiters to integrate intrinsic delay offsets into the decision elements. The unbalanced arbiters are implemented with cross-coupled standard NAND cells and the combination of the NAND cells decides the timing offset between two input signals. Simulations and measurements are conducted to validate the new circuit, which provides variable time difference ranges by controlling the slope of input signals. Since the proposed flash TDC uses only NAND cells in a standard cell library for the arbiters which easily enables the TDC to be used as a soft macro in a typical digital circuit design flow.

In modern CMOS digital design, the noise immunity has come to have an almost equal importance to the power consumption. In the last decade, many low power design schemes have been presented. However, no one can simply judge which one is the best from the noise immunity point of view. In this paper, we investigate the noise immunity of the static CMOS low power design schemes in terms of logic and delay errors caused by different kinds of noise existing in the static CMOS digital circuits. To fulfill the aims of the paper, first a model representing the different sources of noise in deep submicron design is presented. Then the model is applied to the most famous low power design schemes to find out the most robust one with regard to noise. Our results show the advantages of the dual threshold voltage scheme over other schemes from the noise immunity point of view. Moreover, it indicates that noise should be carefully taken into account when designing low power circuits; otherwise circuit performance would be unexpected. The study is carried out on three circuits; each is designed in five different schemes. The analysis is done using HSPICE, assuming 0.18 µm CMOS technology.