IEICE TRANSACTIONS on Electronics
Design for Testability That Reduces Linearity Testing Time of SAR ADCs
Summary :
This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.6 pp.1061-1064
- Publication Date
- 2011/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.1061
- Type of Manuscript
- BRIEF PAPER
- Category
Authors
Tomohiko OGAWA
Haruo KOBAYASHI
Satoshi UEMORI
Yohei TAN
Satoshi ITO
Nobukazu TAKAI
Takahiro J. YAMAGUCHI
Kiichi NIITSU
Keyword
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Tomohiko OGAWA, Haruo KOBAYASHI, Satoshi UEMORI, Yohei TAN, Satoshi ITO, Nobukazu TAKAI, Takahiro J. YAMAGUCHI, Kiichi NIITSU, "Design for Testability That Reduces Linearity Testing Time of SAR ADCs" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 6, pp. 1061-1064, June 2011, doi: 10.1587/transele.E94.C.1061.
Abstract: This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1061/_p
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@ARTICLE{e94-c_6_1061,
author={Tomohiko OGAWA, Haruo KOBAYASHI, Satoshi UEMORI, Yohei TAN, Satoshi ITO, Nobukazu TAKAI, Takahiro J. YAMAGUCHI, Kiichi NIITSU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design for Testability That Reduces Linearity Testing Time of SAR ADCs},
year={2011},
volume={E94-C},
number={6},
pages={1061-1064},
abstract={This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.},
keywords={},
doi={10.1587/transele.E94.C.1061},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - Design for Testability That Reduces Linearity Testing Time of SAR ADCs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1061
EP - 1064
AU - Tomohiko OGAWA
AU - Haruo KOBAYASHI
AU - Satoshi UEMORI
AU - Yohei TAN
AU - Satoshi ITO
AU - Nobukazu TAKAI
AU - Takahiro J. YAMAGUCHI
AU - Kiichi NIITSU
PY - 2011
DO - 10.1587/transele.E94.C.1061
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2011
AB - This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.
ER -
English
