In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.

The scan segmentation method is an efficient solution to deal with the test power problem; However, the use of multiple capture cycles may cause capture violations, thereby leading to fault coverage loss. This issue is much more severe in at-speed testing. In this paper, two scan partition schemes based on complex networks clustering ara proposed to minimize the capture violations without increasing test-data volume and extra area overhead. In the partition process, we use a more accurate notion, spoiled nodes, instead of violation edges to analyse the dependency of flip-flops (ffs), and we use the shortest-path betweenness (SPB) method and the Laplacian-based graph partition method to find the best combination of these flip-flops. Beyond that, the proposed methods can use any given power-unaware set of patterns to test circuits, reducing both shift and capture power in at-speed testing. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed methods.

The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-µm CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.

This paper proposes a method for testing delay faults using a boundary scan circuit in which a time-to-digital converter (TDC) is embedded. The incoming transitions from the other cores or chips are captured at the boundary scan circuit. The TDC circuit is modified to set the initial value for a delay line through which the transition is propagated. The condition for measuring timing slacks of two or more paths is also investigated since the overlap of the signals may occur in the delay line of the TDC in our boundary scan circuit. An experimental IC with the TDC and boundary scan is fabricated and is measured to estimate the delay of some paths measured by the TDC embedded in boundary scan cells. The simulation results for a benchmark circuit with the boundary scan circuit are also shown for the case that timing slacks of multiple paths can be observed even if the signals overlap in the TDC.

This paper describes a high-speed, robust, scalable, and low-cost feed-forward time amplifier that uses phase detectors and variable delay lines. The amplifier works by detecting the time difference between two rising input edges with a phase detector and adjusting the delay of the variable delay line accordingly. A test chip was designed and fabricated in 65 nm CMOS. The measured resulting performance indicates that it is possible to amplify time difference while maintaining high-speed operation.

We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2:1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.

Generally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. The first is that an automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We evaluated our architecture and test configurations using a prototype chip. As a result, the chip was fully tested using our configurations in a short test time. Moreover, our architecture can provide comparable performance to a conventional FPGA architecture.

Digital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRPTM) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and built-in self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as 'soft specifications', are defined.

This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.

A C-testable 4-2 adder tree for an easily testable high-speed multiplier is proposed, and a recursive method for test generation is shown. By using the specific patterns that we call 'alternately inverted patterns,' the adder tree, as well as partial product generators, can be tested with 14 patterns regardless of its operand size under the cell fault model. The test patterns are easily fed through the partial product generators. The hardware overhead of the 4-2 adder tree with partial product generators for a 64-bit multiplier is about 15%. By using a previously proposed easily testable adder as the final adder, we can obtain an easily testable high-speed multiplier.

We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.

Proposed in this paper is a low power BIST architecture using the pattern mapping method based on the transition freezing method. The transition freezing method generates frozen patterns dynamically according to the transition tendency of an LFSR. This leads to an average power reduction of 60%. However, the patterns have limitations of 100% fault coverage due to random resistant faults. Therefore, in this paper, those faults are detected by mapping useless patterns among frozen patterns to the patterns generated by an ATPG. Throughout the scheme, 100% fault coverage is achieved. Moreover, we have reduced the amount of applied patterns, the test time, and the power dissipation.

This paper presents a selective scan slice grouping technique for test data compression. In conventional selective encoding methods, the existence of a conflict bit contributes to large encoding data. However, many conflict bits are efficiently removed using the scan slice grouping technique, which leads to a dramatic improvement of encoding efficiency. Experiments performed with large ITC'99 benchmark circuits presents the effectiveness of the proposed technique and the test data volume is reduced up to 92% compared to random-filled test patterns.

In this paper, we present an efficient low power scan test technique which simultaneously reduces both average and peak power consumption. The selective scan chain activation scheme removes unnecessary scan chain utilization during the scan shift and capture operations. Statistical scan cell reordering enables efficient scan chain removal. The experimental results demonstrated that the proposed method constantly reduces the average and peak power consumption during scan testing.

This paper presents a grouped scan slice encoding technique using scan slice repetition to simultaneously reduce test data volume and test application time. Using this method, many scan slices that would be incompatible with the conventional selective scan slice method can be encoded as compatible scan slices. Experiments were performed with ISCAS'89 and ITC'99 benchmark circuits, and results show the effectiveness of the proposed method.

This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.

Testing PLLs (phase-locked loops) is becoming an important issue that affects both time-to-market and production cost of electronic systems. Though a PLL is the most common mixed-signal building block, it is very difficult to test due to internal analog blocks and signals. In this paper, we propose a new PLL BIST (built-in self test) using the distorted frequency detector that uses only internal digital signals. The proposed BIST does not need to load any analog nodes of the PLL. Therefore, it provides an efficient defect-oriented structural test scheme, reduced area overhead, and improved test quality compared with previous approaches.

In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency, that is, it completely avoids the error masking. Moreover, the proposed method has no performance degradation (adds only observation points) and enables at-speed testing.

A tri-template-based codes (TTBC) method is proposed to reduce test cost of intellectual property (IP) cores. In order to reduce test data volume (TDV), the approach utilizes three templates, i.e., all 0, all 1, and the previously applied test data, for generating the subsequent test data by flipping the inconsistent bits. The approach employs a small number of test channels I to supply a large number of internal scan chains 2I-3 such that it can achieve significant reduction in test application time (TAT). Furthermore, as a non-intrusive and automatic test pattern generation (ATPG) independent solution, the approach is suitable for IP core testing because it requires neither redesign of the core under test (CUT) nor running any additional ATPG for the encoding procedure. In addition, the decoder has low hardware overhead, and its design is independent of the CUT and the given test set. Theoretical analysis and experimental results for ISCAS 89 benchmark circuits have proven the efficiency of the proposed approach.

Multi-context FPGAs allow very quick reconfiguration by storing multiple configuration data at the same time. While testing for FPGAs with single-context memories has already been studied by many researchers, testing for multi-context FPGAs has not been proposed yet. This paper presents an architecture of testable multi-context FPGAs. In the proposed multi-context FPGA, configuration data stored in a context can be copied into another context. This paper also shows testing of the proposed multi-context FPGA. The proposed testing uses the testing for the traditional FPGAs with single-context. The testing is capable of detecting single stuck-at faults and single open faults which affect normal operations. The number of test configurations for the proposed testing is at most two more than that for the testing of FPGAs with single-context memories. The area overhead of the proposed architecture is 7% and 4% of the area of a multi-context FPGA without the proposed architecture when the number of contexts in a configuration memory is 8 and 16, respectively.