IEICE TRANSACTIONS on Information
An Easily Testable Routing Architecture and Prototype Chip
Summary :
Generally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. The first is that an automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We evaluated our architecture and test configurations using a prototype chip. As a result, the chip was fully tested using our configurations in a short test time. Moreover, our architecture can provide comparable performance to a conventional FPGA architecture.
- Publication
- IEICE TRANSACTIONS on Information Vol.E95-D No.2 pp.303-313
- Publication Date
- 2012/02/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E95.D.303
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Architecture
Authors
Kazuki INOUE
Masahiro KOGA
Motoki AMAGASAKI
Masahiro IIDA
Yoshinobu ICHIDA
Mitsuro SAJI
Jun IIDA
Toshinori SUEYOSHI
Keyword
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Kazuki INOUE, Masahiro KOGA, Motoki AMAGASAKI, Masahiro IIDA, Yoshinobu ICHIDA, Mitsuro SAJI, Jun IIDA, Toshinori SUEYOSHI, "An Easily Testable Routing Architecture and Prototype Chip" in IEICE TRANSACTIONS on Information,
vol. E95-D, no. 2, pp. 303-313, February 2012, doi: 10.1587/transinf.E95.D.303.
Abstract: Generally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. The first is that an automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We evaluated our architecture and test configurations using a prototype chip. As a result, the chip was fully tested using our configurations in a short test time. Moreover, our architecture can provide comparable performance to a conventional FPGA architecture.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E95.D.303/_p
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@ARTICLE{e95-d_2_303,
author={Kazuki INOUE, Masahiro KOGA, Motoki AMAGASAKI, Masahiro IIDA, Yoshinobu ICHIDA, Mitsuro SAJI, Jun IIDA, Toshinori SUEYOSHI, },
journal={IEICE TRANSACTIONS on Information},
title={An Easily Testable Routing Architecture and Prototype Chip},
year={2012},
volume={E95-D},
number={2},
pages={303-313},
abstract={Generally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. The first is that an automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We evaluated our architecture and test configurations using a prototype chip. As a result, the chip was fully tested using our configurations in a short test time. Moreover, our architecture can provide comparable performance to a conventional FPGA architecture.},
keywords={},
doi={10.1587/transinf.E95.D.303},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - An Easily Testable Routing Architecture and Prototype Chip
T2 - IEICE TRANSACTIONS on Information
SP - 303
EP - 313
AU - Kazuki INOUE
AU - Masahiro KOGA
AU - Motoki AMAGASAKI
AU - Masahiro IIDA
AU - Yoshinobu ICHIDA
AU - Mitsuro SAJI
AU - Jun IIDA
AU - Toshinori SUEYOSHI
PY - 2012
DO - 10.1587/transinf.E95.D.303
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2012
AB - Generally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. The first is that an automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We evaluated our architecture and test configurations using a prototype chip. As a result, the chip was fully tested using our configurations in a short test time. Moreover, our architecture can provide comparable performance to a conventional FPGA architecture.
ER -
English
