Bit error rates (BER) for playback of (1,7) code employed in optical disc recording were simulated using an ideal (Gaussian) playback waveform, with playback being performed by PRML (Partial Response Maximum-Likelihood) combining a partial response equalizer and a double clock weighted Viterbi decoder. It was found that best BER occurs for PR(2,3,3,2) +7/10 level Viterbi decoding at a weighted value of w = 0.5 for data consisting of 107 symbols. For a minimum bit length of 0.28 µm, BER of 10-4 and less than 10-6 was obtained for SN ratios of 15.6 dB and 17.7 dB, respectively. And for a minimum bit length of 0.26 µm, BER of 10-4 and less than 10-6 was obtained for SN ratios of 16.7 dB and 18.8 dB, respectively. These results demonstrate the feasibility of a minimum bit length of 0.26 µm in current optical disc recorders.

Wide-area VM migration is a technology with potential to aid IT services recovery since it can be used to evacuate virtualized servers to safe locations upon a critical disaster. However, the amount of data involved in a wide-area VM migration is substantially larger compared to VM migrations within LAN due to the need to transfer virtualized storage in addition to memory and CPU states. This increase of data makes it challenging to relocate VMs under a limited time window with electrical power. In this paper, we propose a mechanism to improve live storage migration across WAN. The key idea is to reduce the amount of data to be transferred by proactively caching virtual disk blocks to a backup site during regular VM operation. As a result of pre-cached disk blocks, the proposed mechanism can dramatically reduce the amount of data and consequently the time required to live migrate the entire VM state. The mechanism was evaluated using a prototype implementation under different workloads and network conditions, and we confirmed that it dramatically reduces the time to complete a VM live migration. By using the proposed mechanism, it is possible to relocate a VM from Japan to the United States in just under 40 seconds. This relocation would otherwise take over 1500 seconds, demonstrating that the proposed mechanism was able to reduce the migration time by 97.5%.

This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.

Image quality depends on the randomness of the k-space signal under-sampling in compressed sensing MRI (CS-MRI), especially for two-dimensional image acquisition. We investigate the feasibility of non-random signal under-sampling CS-MRI to stabilize the quality of reconstructed images and avoid arbitrariness in sampling point selection. Regular signal under-sampling for the phase-encoding direction is adopted, in which sampling points are chosen at equal intervals for the phase-encoding direction while varying the sampling density. Curvelet transform was adopted to remove the aliasing artifacts due to regular signal under-sampling. To increase the incoherence between the measurement matrix and the sparsifying transform function, the scale of the curvelet transform was varied in each iterative image reconstruction step. We evaluated the obtained images by the peak-signal-to-noise ratio and root mean squared error in localized 3×3 pixel regions. Simulation studies and experiments showed that the signal-to-noise ratio and the structural similarity index of reconstructed images were comparable to standard random under-sampling CS. This study demonstrated the feasibility of non-random under-sampling based CS by using the multi-scale curvelet transform as a sparsifying transform function. The technique may help to stabilize the obtained image quality in CS-MRI.

This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.

Postcopy live migration is a promising alternative of virtual machine (VM) migration, which transfers memory pages after switching the execution host of a VM. It allows a shorter and more deterministic migration time than precopy migration. There is, however, a possibility that postcopy migration would degrade VM performance just after switching the execution host. In this paper, we propose a performance improvement technique of postcopy migration, extending the para-virtualized page fault mechanism of a virtual machine monitor. When the guest operating system accesses a not-yet-transferred memory page, our proposed mechanism allows the guest kernel to defer the execution of the current process until the page data is transferred. In parallel with the page transfer, the guest kernel can yield VCPU to other active processes. We implemented the proposed technique in our postcopy migration mechanism for Qemu/KVM. Through experiments, we confirmed that our technique successfully alleviated performance degradation of postcopy migration for web server and database benchmarks.

The key elements of sub-100 nm MOSFET modeling for circuit simulation are accurate representation of new physical phenomena arising from advancing technologies and numerical efficacy. We summarize the history of MOSFET modeling, and address difficulties faced by conventional methods. The advantage of the surface-potential-based approach will be emphasized. Perspectives for next generations will be also discussed.

The concepts of programmable switches and software-defined networking (SDN) give developers flexible and deep control over the behavior of switches. We expect these concepts to dramatically improve the functionality of switches. In this paper, we focus on the concept of Deeply Programmable Networks (DPN), where data planes are programmable, and application switches based on DPN. We then propose a method to improve the performance of a key-value store (KVS) through an application switch. First, we explain the DPN and application switches. The DPN is a network that makes not only control planes but also data planes programmable. An application switch is a switch that implements some functions of network applications, such as database management system (DBMS). Second, we propose a method to improve the performance of Cassandra, one of the most popular key-value based DBMS, by implementing a caching function in a switch in a dedicated network such as a data center. The proposed method is expected to be effective even though it is a simple and traditional way because it is in the data path and the center of the network application. Third, we implement a switch with the caching function, which monitors the accessed data described in packets (Ethernet frames) and dynamically replaces the cached data in the switch, and then show that the proposed caching switch can significantly improve the KVS transaction performance with this implementation. In the case of our evaluation, our method improved the KVS transaction throughput by up to 47%.

A 12×16-element corporate-feed slot array is presented. The corporate-feed circuit for the 12×16-elemtent array consists of cross-junctions and asymmetric T-junctions, whereas the conventional one is limited to arrays of 2m×2n slots by its use of symmetric T-junctions. Simulations of the 12×16-element array show a 7.6% bandwidth for reflection less than -14dB. A 31.7-dBi gain with an antenna efficiency of 82.6% is obtained at the design frequency of 61.5GHz. The 12×16-element array is fabricated by diffusion bonding of laminated thin metal plates. Measurements indicate 31.1-dBi gain with 71.9% antenna efficiency at 61.5GHz.