This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.
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Takuya YAGI, Kunihiko USUI, Tatsuji MATSUURA, Satoshi UEMORI, Satoshi ITO, Yohei TAN, Haruo KOBAYASHI, "Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 7, pp. 1233-1236, July 2011, doi: 10.1587/transele.E94.C.1233.
Abstract: This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1233/_p
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@ARTICLE{e94-c_7_1233,
author={Takuya YAGI, Kunihiko USUI, Tatsuji MATSUURA, Satoshi UEMORI, Satoshi ITO, Yohei TAN, Haruo KOBAYASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme},
year={2011},
volume={E94-C},
number={7},
pages={1233-1236},
abstract={This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.},
keywords={},
doi={10.1587/transele.E94.C.1233},
ISSN={1745-1353},
month={July},}
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TY - JOUR
TI - Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme
T2 - IEICE TRANSACTIONS on Electronics
SP - 1233
EP - 1236
AU - Takuya YAGI
AU - Kunihiko USUI
AU - Tatsuji MATSUURA
AU - Satoshi UEMORI
AU - Satoshi ITO
AU - Yohei TAN
AU - Haruo KOBAYASHI
PY - 2011
DO - 10.1587/transele.E94.C.1233
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2011
AB - This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.
ER -