This work presents the thermal noise analysis results of ring amplifiers in the MDAC of cyclic ADC. Ring amplifier is an alternative closed-loop structure for residual signal amplification with MDAC, and two types of ring amplifiers: pseudo-differential and fully-differential ring-amplifiers are considered for the implementation of MDAC in cyclic ADC. Theoretical analysis results show that power of thermal noise in MDAC with a pseudo-differential amplifier is much higher than that with a fully-differential ring-amplifier. SPICE simulation results with transient noise analyses also show the similar trend. Experimental prototype cyclic ADCs in 65nm CMOS technology are implemented with the same architecture and the same circuit components except for amplifiers. Comparison of the measured results of the two ADCs confirms the validity of the theoretical analysis results.

A new gain enhancement technique for an operational amplifier (opamp) using a replica amplifier is presented to reduce a sensitivity of a gain mismatch between the main amplifier and the replica amplifier which limits a gain-enhancement factor in the conventional replica-amp techniques. In the proposed technique, the replica amplifier is used to only amplify an error voltage of the main amplifier. The outputs of the main amplifier and the replica amplifier are added to cancel the error voltage of the main amplifier. The proposed technique can also achieve a higher output voltage swing because the replica amplifier amplifies only the error voltage. In case of using a fully-differential common-source opamp for the main amplifier and a telescopic opamp for the replica amplifier, Monte Carlo simulation at 100 iterations shows that the proposed amplifier has almost the same gain variation with 15.5dB gain enhancement and about five times output voltage swing expanding for a supply voltage of 1.2V compared with the single closed-loop amplifier using the telescopic opamp.

A false lock free delay-locked loop(DLL) achieving a wide frequency operation and a fine timing resolution is presented. A novel false lock detection technique is proposed to solve the trade-off between a wide frequency range and false locks. This technique enables a fine timing resolution even at a high frequency. In addition, the duty cycle of the input clock is not required to be 50%. This technique is applied to the DLLs in analog front-end LSIs of digital camera systems, with a range of 465 MHz (16) and a timing resolution of 9(40 stages).

A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.

A low-power-consumption 6-bit pipelined analog-to-digital converter for use in a BluetoothTM RF transceiver has been developed. The RF transceiver chip was fabricated using a 0.35-µm BiCMOS process, and the A/D converter is based on CMOS technology for digital logic. To reduce the power consumption of the converter, we used a look-ahead pipeline architecture to reduce the required settling time of an amplifier in the critical path of the converter. We show that through this reduction, amplifier power consumption of 600 µA can be reduced to 250 µA to achieve a 13-MHz conversion rate. We have also developed a low-power two-capacitor switched-capacitor common-mode feedback circuit which enables an offset cancellation of an amplifier during the reset phase. Offset cancellation is used in each stage of the S/H amplifier to reduce the overall offset of the converter. It achieves an effective number of bits of 5.7 at a conversion rate of 13 Msps and 5.0 at 26 Msps. The residual offset of the converter is only 4 mV. It has a low total current consumption of 3.2 mA at 13 Msps and a supply voltage of 2.8 V.

A 12-bit 1.25MS/s cyclic analog-to-digital converter (ADC) is designed and fabricated in 90nm CMOS technology, and only occupies an active area as small as 0.037mm2. The proposed ADC is composed of a non-binary AD convertion stage, and a on-chip non-binary-to-binary digital block includes a built-in radix-value self-estimation scheme. Therefore, althouh a non-binary convertion architechture is adopted, the proposed ADC is the same as other stand-alone binary ADCs. The redundancy of non-binary 1-bit/step architecture relaxes the accuracy requirement on analog components of ADC. As a result, the implementation of analog circuits such as amplifier and comparator becomes simple, and high-density Metal-Oxide-Metal (MOM) capacitors can be used to achieve a small chip area. Furthermore, the novel radix-value self-estimation technique can be realized by only simple logic circuits without any extra analog input, so that the total active area of ADC is dramatically reduced. The prototype ADC achieves a measured peak signal-to-noise-and-distortion-ratio (SNDR) of 62.3dB using a poor DC gain amplifier as low as 45dB and MOM capacitors without any careful layout techniques to improve the capacitor matching. The proposed ADC dissipated 490µW in analog circuits at 1.4V power supply and 1.25Msps (20MHz clocking). The measured DNL is +0.94/-0.71LSB and INL is +1.9/-1.2LSB at 30kHz sinusoidal input.

Very-low-voltage 1.2-V mixed-signal CMOS technology is a device/circuit solution aimed at ultra-low-power portable systems such as digital cellular terminals and PDAs. We have developed an experimental 1.2-V mixed analog and digital LSI circuit/device technology. This technology is based on a new transistor structure that has a 0.3-µm gate length and a low Vth of 0.4 V, and that suppresses the short-channel effect. In this paper, we will mainly discuss low-voltage analog circuit design that uses this technology. We show that low Vth is essential not only to digital circuits, but also to 1.2-V analog amplifier, A/D converter and analog switch designs. To achieve high-conversion rate A/D converters, a pipeline architecture is used for low-voltage operation. To increase the attainable gain-bandwidth of the operational amplifier of the converter, a feedforward phase-compensated three-stage amplifier is proposed. The addition of a feedforward capacitor allows a high frequency signal to pass directly to the second stage, which optimizes use of the second stage bandwidth. Pole-zero canceling is used to achieve a fast settling of the amplifier. Although gain precision is degraded by the positive feedback through the feedforward capacitor, this can be offset by increasing the equivalent second-stage gain with an inner feedforward compensated amplifier. The gain-bandwidth of the proposed double feedforward amplifier is two to three times wider than with the conventional Miller compensation. With these techniques, we used 1.2-V mixed-signal CMOS technology to create a basic logic gate with a 400-ps delay and 0.4-µW/MHz power, and a 9-bit 2-Msample/s pipeline A/D converter with power dissipation of only 4 mW.

A 10-bit 3-Msample/s multibit cyclic A/D converter for mixed-signal LSIs with a small chip-area of 1.5 mm2 and low power consumption of 10.8 mW with a 2.7-V power supply was realized using a 0.8-µm CMOS process. This ADC module is designed for high-speed servo-controller LSIs used in hard-disk-drive systems. We found that three-cycle cyclic conversion (four bit, three bit+(one redundant bit), and three bit+(one redundant bit)) was optimal for achieving 10-bit resolution with a small chip-area and low power consumption given a required conversion time of 0.33 µs. Our multipath architecture cut power consumption by 30% compared to conventional cyclic A/D converters. By adding one signal path between the residue amplifier and the four bit subADC, the settling timing requirement can be relaxed, and the amplifier's power consumption thus reduced.

This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC conversion steps than a binary search algorithm, but we show that the sampling speed of an SAR ADC using this algorithm can be faster than that of a conventional binary-search SAR ADC -- because the latter must wait for the settling time of the DAC inside the SAR ADC.

We have proposed a new low-IF transceiver architecture to simultaneously achieve both a small chip area and good minimum input sensitivity. The distinctive point of the receiver architecture is that we replace the complicated high-order analog filter for channel selection with the combination of a simple low-order analog filter and a sharp digital band-pass filter. We also proposed a high-speed convergence AGC (automatic gain controller) and a demodulation block to realize the proposed digital architecture. For the transceiver, we further reduce the chip area by applying a new form of direct modulation for the VCO. Since conventional VCO direct modulation tends to suffer from variation of the modulation index with frequency, we have developed a new compensation technique that minimizes this variation, and designed the low-phase noise VCO with a new biasing method to achieve large PSRR (power-supply rejection ratio) for oscillation frequency. The test chip was fabricated in 0.35-µm BiCMOS. The chip size was 3 3 mm2; this very small area was realized by the advantages of the proposed transceiver architecture. The transceiver also achieved good minimum input sensitivity of -85 dBm and showed interference performance that satisfied the requirements of the Bluetooth standard.

A method called "active guard band filtering" is proposed for reducing substrate noise in analog and digital mixed-signal integrated circuits. A noise cancellation signal having an inverse value to the substrate noise is actively input into a guard band to suppress the substrate noise. An operational amplifier produces the noise cancellation signal based upon the substrate noise detected by one guard band and feeds this signal through another quard band into the substrate. This is done within the amplifier feedback loop, which includes the guard bands and the substrate. The noise suppression effect was measured by using 0.8µm CMOS test chip. Using active guard band filtering suppressed substrate noise to -40 dB of the original non-canceled noise level at 8 MHz. The noise suppression effect was also observed at frequencies up to 20MHz, with an external operational amplifier. The influence of parasitic impedance was found to be a key factor in noise suppression. An active guard band filter with an on-chip noise cancellation circuit will be even more effective for high frequencies, because it eliminates parasitic impedance due to external components.

Analog-to-Digital converters (ADCs) for video applications have made exciting progress in miniaturization and power reduction in the past 20 years. This paper mainly describes the key technologies for miniaturization and power reduction of 10-bit video-frequency ADCs. By reviewing useful architectures and circuit schemes for video-frequency ADCs, self-calibration techniques and interleaving techniques are surveyed. The subranging pipeline look-ahead ADC architecture is introduced. It has a potential for reducing power consumption and improving conversion rate when minute deep submicron CMOS devices are used with low supply voltage.

C-C successive approximation register analog-to-digital converter (C-C SAR-ADC) is space-saving architecture compared to SAR-ADC with binary weighted capacitive digital-to-analog converter (CDAC). However, the accuracy of C-C SAR-ADC is degraded due to parasitic capacitance of floating nodes. This paper proposes an algorithm calibrating the non-linearity by γ-estimation to accurately estimate radix greater than 2 required to realize C-C SAR-ADC. Behavioral analyses show that the radix γ-estimation error become within 1.5, 0.4 and 0.1% in case of 8-, 10- and 12-bit resolution ADC, respectively. SPICE simulations show that the γ-estimation satisfies the requirement of 10-bit resolution C-C SAR-ADC. The C-C SAR-ADC using γ-estimation achieves 9.72bit of ENOB, 0.8/-0.5LSB and 0.5/-0.4LSB of DNL/INL.

This paper proposes a new architecture for multibit complex bandpass ΔΣAD modulators with built-in Switched-Capacitor (SC) circuits for application to Low-IF receivers such as used for Bluetooth and WLAN. In the realization of complex bandpass ΔΣAD modulators, we face the following problems: (i) SNR of AD converter is deteriorated by mismatches between internal analog I and Q paths. (ii) Layout design becomes complicated because of signal lines crossing by complex filter and feedback from DAC for I and Q paths in the complex modulator, and this increases required chip area. We propose a new structure for a complex bandpass ΔΣAD modulator which can be completely divided into two paths without layout crossing, and solves the problems mentioned above. The two parts of signal paths and circuits in the modulator are changed for I and Q while CLK is changed for High/Low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain timing, and they are switched by multiplexers to those used for Q and I paths at another timing. Therefore the influence from mismatches between I and Q paths is reduced by dynamic matching. As a result, the modulator is divided into two separate parts without crossing signal lines between I and Q paths and its layout design can be greatly simplified compared with conventional modulators. We have conducted MATLAB simulations to confirm the effectiveness of the proposed structure.

This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.

We have designed, fabricated and measured a second-order multibit switched-capacitor complex bandpass ΔΣAD modulator to evaluate our new algorithms and architecture. We propose a new structure of a complex bandpass filter in the forward path with I, Q dynamic matching, that is equivalent to the conventional one but can be divided into two separate parts. As a result, the ΔΣ modulator, which employs our proposed complex filter can also be divided into two separate parts, and there are no signal lines crossing between the upper and lower paths formed by complex filters and feedback DACs. Therefore, the layout design of the modulator can be simplified. The two sets of signal paths and circuits in the modulator are changed between I and Q while CLK is changed between high and low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain period of time, and they are switched by multiplexers to those used for Q and I paths at another period of time. In this manner, the effect of mismatches between I and Q paths is reduced. Two nine-level quantizers and four DACs are used in the modulator for low-power implementations and higher signal-to-noise-and-distortion (SNDR), but the nonlinearities of DACs are not noise-shaped and the SNDR of the ΔΣAD modulator degrades. We have also employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized by just adding simple digital circuitry. To evaluate these algorithms and architecture, we have implemented a modulator using 0.18 µm CMOS technology for operation at 2.8 V power supply; it achieves a measured peak SNDR of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm2. These experimental results demonstrate the effectiveness of the above two algorithms, and the algorithms may be extended to other complex bandpass ΔΣAD modulators for application to low-IF receivers in wireless communication systems.