IEICE TRANSACTIONS on Fundamentals
Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation
Summary :
C-C successive approximation register analog-to-digital converter (C-C SAR-ADC) is space-saving architecture compared to SAR-ADC with binary weighted capacitive digital-to-analog converter (CDAC). However, the accuracy of C-C SAR-ADC is degraded due to parasitic capacitance of floating nodes. This paper proposes an algorithm calibrating the non-linearity by γ-estimation to accurately estimate radix greater than 2 required to realize C-C SAR-ADC. Behavioral analyses show that the radix γ-estimation error become within 1.5, 0.4 and 0.1% in case of 8-, 10- and 12-bit resolution ADC, respectively. SPICE simulations show that the γ-estimation satisfies the requirement of 10-bit resolution C-C SAR-ADC. The C-C SAR-ADC using γ-estimation achieves 9.72bit of ENOB, 0.8/-0.5LSB and 0.5/-0.4LSB of DNL/INL.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E104-A No.2 pp.516-524
- Publication Date
- 2021/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.2020GCP0008
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
Satoshi SEKINE
Tokyo University of Science
Tatsuji MATSUURA
Tokyo University of Science
Ryo KISHIDA
Tokyo University of Science
Akira HYOGO
Tokyo University of Science
Keyword
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Satoshi SEKINE, Tatsuji MATSUURA, Ryo KISHIDA, Akira HYOGO, "Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation" in IEICE TRANSACTIONS on Fundamentals,
vol. E104-A, no. 2, pp. 516-524, February 2021, doi: 10.1587/transfun.2020GCP0008.
Abstract: C-C successive approximation register analog-to-digital converter (C-C SAR-ADC) is space-saving architecture compared to SAR-ADC with binary weighted capacitive digital-to-analog converter (CDAC). However, the accuracy of C-C SAR-ADC is degraded due to parasitic capacitance of floating nodes. This paper proposes an algorithm calibrating the non-linearity by γ-estimation to accurately estimate radix greater than 2 required to realize C-C SAR-ADC. Behavioral analyses show that the radix γ-estimation error become within 1.5, 0.4 and 0.1% in case of 8-, 10- and 12-bit resolution ADC, respectively. SPICE simulations show that the γ-estimation satisfies the requirement of 10-bit resolution C-C SAR-ADC. The C-C SAR-ADC using γ-estimation achieves 9.72bit of ENOB, 0.8/-0.5LSB and 0.5/-0.4LSB of DNL/INL.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2020GCP0008/_p
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@ARTICLE{e104-a_2_516,
author={Satoshi SEKINE, Tatsuji MATSUURA, Ryo KISHIDA, Akira HYOGO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation},
year={2021},
volume={E104-A},
number={2},
pages={516-524},
abstract={C-C successive approximation register analog-to-digital converter (C-C SAR-ADC) is space-saving architecture compared to SAR-ADC with binary weighted capacitive digital-to-analog converter (CDAC). However, the accuracy of C-C SAR-ADC is degraded due to parasitic capacitance of floating nodes. This paper proposes an algorithm calibrating the non-linearity by γ-estimation to accurately estimate radix greater than 2 required to realize C-C SAR-ADC. Behavioral analyses show that the radix γ-estimation error become within 1.5, 0.4 and 0.1% in case of 8-, 10- and 12-bit resolution ADC, respectively. SPICE simulations show that the γ-estimation satisfies the requirement of 10-bit resolution C-C SAR-ADC. The C-C SAR-ADC using γ-estimation achieves 9.72bit of ENOB, 0.8/-0.5LSB and 0.5/-0.4LSB of DNL/INL.},
keywords={},
doi={10.1587/transfun.2020GCP0008},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 516
EP - 524
AU - Satoshi SEKINE
AU - Tatsuji MATSUURA
AU - Ryo KISHIDA
AU - Akira HYOGO
PY - 2021
DO - 10.1587/transfun.2020GCP0008
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E104-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2021
AB - C-C successive approximation register analog-to-digital converter (C-C SAR-ADC) is space-saving architecture compared to SAR-ADC with binary weighted capacitive digital-to-analog converter (CDAC). However, the accuracy of C-C SAR-ADC is degraded due to parasitic capacitance of floating nodes. This paper proposes an algorithm calibrating the non-linearity by γ-estimation to accurately estimate radix greater than 2 required to realize C-C SAR-ADC. Behavioral analyses show that the radix γ-estimation error become within 1.5, 0.4 and 0.1% in case of 8-, 10- and 12-bit resolution ADC, respectively. SPICE simulations show that the γ-estimation satisfies the requirement of 10-bit resolution C-C SAR-ADC. The C-C SAR-ADC using γ-estimation achieves 9.72bit of ENOB, 0.8/-0.5LSB and 0.5/-0.4LSB of DNL/INL.
ER -
English
