A 3.2-mA 6-Bit Pipelined A/D Coverter for a Bluetooth RF Transceiver

Tatsuji MATSUURA; Junya KUDOH; Eiki IMAIZUMI

A 3.2-mA 6-Bit Pipelined A/D Coverter for a Bluetooth RF Transceiver

Tatsuji MATSUURA, Junya KUDOH, Eiki IMAIZUMI

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A low-power-consumption 6-bit pipelined analog-to-digital converter for use in a Bluetooth^TM RF transceiver has been developed. The RF transceiver chip was fabricated using a 0.35-µm BiCMOS process, and the A/D converter is based on CMOS technology for digital logic. To reduce the power consumption of the converter, we used a look-ahead pipeline architecture to reduce the required settling time of an amplifier in the critical path of the converter. We show that through this reduction, amplifier power consumption of 600 µA can be reduced to 250 µA to achieve a 13-MHz conversion rate. We have also developed a low-power two-capacitor switched-capacitor common-mode feedback circuit which enables an offset cancellation of an amplifier during the reset phase. Offset cancellation is used in each stage of the S/H amplifier to reduce the overall offset of the converter. It achieves an effective number of bits of 5.7 at a conversion rate of 13 Msps and 5.0 at 26 Msps. The residual offset of the converter is only 4 mV. It has a low total current consumption of 3.2 mA at 13 Msps and a supply voltage of 2.8 V.

Publication: IEICE TRANSACTIONS on Electronics Vol.E85-C No.8 pp.1538-1545

Publication Date: 2002/08/01

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Type of Manuscript: Special Section PAPER (Special Issue on High-Performance Analog Integrated Circuits)

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Tatsuji MATSUURA, Junya KUDOH, Eiki IMAIZUMI, "A 3.2-mA 6-Bit Pipelined A/D Coverter for a Bluetooth RF Transceiver" in IEICE TRANSACTIONS on Electronics, vol. E85-C, no. 8, pp. 1538-1545, August 2002, doi: .
Abstract: A low-power-consumption 6-bit pipelined analog-to-digital converter for use in a Bluetooth^TM RF transceiver has been developed. The RF transceiver chip was fabricated using a 0.35-µm BiCMOS process, and the A/D converter is based on CMOS technology for digital logic. To reduce the power consumption of the converter, we used a look-ahead pipeline architecture to reduce the required settling time of an amplifier in the critical path of the converter. We show that through this reduction, amplifier power consumption of 600 µA can be reduced to 250 µA to achieve a 13-MHz conversion rate. We have also developed a low-power two-capacitor switched-capacitor common-mode feedback circuit which enables an offset cancellation of an amplifier during the reset phase. Offset cancellation is used in each stage of the S/H amplifier to reduce the overall offset of the converter. It achieves an effective number of bits of 5.7 at a conversion rate of 13 Msps and 5.0 at 26 Msps. The residual offset of the converter is only 4 mV. It has a low total current consumption of 3.2 mA at 13 Msps and a supply voltage of 2.8 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_8_1538/_p

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@ARTICLE{e85-c_8_1538,
author={Tatsuji MATSUURA, Junya KUDOH, Eiki IMAIZUMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 3.2-mA 6-Bit Pipelined A/D Coverter for a Bluetooth RF Transceiver},
year={2002},
volume={E85-C},
number={8},
pages={1538-1545},
abstract={A low-power-consumption 6-bit pipelined analog-to-digital converter for use in a Bluetooth^TM RF transceiver has been developed. The RF transceiver chip was fabricated using a 0.35-µm BiCMOS process, and the A/D converter is based on CMOS technology for digital logic. To reduce the power consumption of the converter, we used a look-ahead pipeline architecture to reduce the required settling time of an amplifier in the critical path of the converter. We show that through this reduction, amplifier power consumption of 600 µA can be reduced to 250 µA to achieve a 13-MHz conversion rate. We have also developed a low-power two-capacitor switched-capacitor common-mode feedback circuit which enables an offset cancellation of an amplifier during the reset phase. Offset cancellation is used in each stage of the S/H amplifier to reduce the overall offset of the converter. It achieves an effective number of bits of 5.7 at a conversion rate of 13 Msps and 5.0 at 26 Msps. The residual offset of the converter is only 4 mV. It has a low total current consumption of 3.2 mA at 13 Msps and a supply voltage of 2.8 V.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - A 3.2-mA 6-Bit Pipelined A/D Coverter for a Bluetooth RF Transceiver
T2 - IEICE TRANSACTIONS on Electronics
SP - 1538
EP - 1545
AU - Tatsuji MATSUURA
AU - Junya KUDOH
AU - Eiki IMAIZUMI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2002
AB - A low-power-consumption 6-bit pipelined analog-to-digital converter for use in a Bluetooth^TM RF transceiver has been developed. The RF transceiver chip was fabricated using a 0.35-µm BiCMOS process, and the A/D converter is based on CMOS technology for digital logic. To reduce the power consumption of the converter, we used a look-ahead pipeline architecture to reduce the required settling time of an amplifier in the critical path of the converter. We show that through this reduction, amplifier power consumption of 600 µA can be reduced to 250 µA to achieve a 13-MHz conversion rate. We have also developed a low-power two-capacitor switched-capacitor common-mode feedback circuit which enables an offset cancellation of an amplifier during the reset phase. Offset cancellation is used in each stage of the S/H amplifier to reduce the overall offset of the converter. It achieves an effective number of bits of 5.7 at a conversion rate of 13 Msps and 5.0 at 26 Msps. The residual offset of the converter is only 4 mV. It has a low total current consumption of 3.2 mA at 13 Msps and a supply voltage of 2.8 V.
ER -