IEICE TRANSACTIONS on Electronics
A Small-Chip-Area Transceiver IC for Bluetooth Featuring a Digital Channel-Selection Filter
Summary :
We have proposed a new low-IF transceiver architecture to simultaneously achieve both a small chip area and good minimum input sensitivity. The distinctive point of the receiver architecture is that we replace the complicated high-order analog filter for channel selection with the combination of a simple low-order analog filter and a sharp digital band-pass filter. We also proposed a high-speed convergence AGC (automatic gain controller) and a demodulation block to realize the proposed digital architecture. For the transceiver, we further reduce the chip area by applying a new form of direct modulation for the VCO. Since conventional VCO direct modulation tends to suffer from variation of the modulation index with frequency, we have developed a new compensation technique that minimizes this variation, and designed the low-phase noise VCO with a new biasing method to achieve large PSRR (power-supply rejection ratio) for oscillation frequency. The test chip was fabricated in 0.35-µm BiCMOS. The chip size was 3
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E87-C No.6 pp.878-887
- Publication Date
- 2004/06/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
- Category
Authors
Masaru KOKUBO
Masaaki SHIDA
Takashi OSHIMA
Yoshiyuki SHIBAHARA
Tatsuji MATSUURA
Kazuhiko KAWAI
Takefumi ENDO
Katsumi OSAKI
Hiroki SONODA
Katsumi YAMAMOTO
Masaharu MATSUOKA
Takao KOBAYASHI
Takaaki HEMMI
Junya KUDOH
Hirokazu MIYAGAWA
Hiroto UTSUNOMIYA
Yoshiyuki EZUMI
Kunio TAKAYASU
Jun SUZUKI
Shinya AIZAWA
Mikihiko MOTOKI
Yoshiyuki ABE
Takao KUROSAWA
Satoru OOKAWARA
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Masaru KOKUBO, Masaaki SHIDA, Takashi OSHIMA, Yoshiyuki SHIBAHARA, Tatsuji MATSUURA, Kazuhiko KAWAI, Takefumi ENDO, Katsumi OSAKI, Hiroki SONODA, Katsumi YAMAMOTO, Masaharu MATSUOKA, Takao KOBAYASHI, Takaaki HEMMI, Junya KUDOH, Hirokazu MIYAGAWA, Hiroto UTSUNOMIYA, Yoshiyuki EZUMI, Kunio TAKAYASU, Jun SUZUKI, Shinya AIZAWA, Mikihiko MOTOKI, Yoshiyuki ABE, Takao KUROSAWA, Satoru OOKAWARA, "A Small-Chip-Area Transceiver IC for Bluetooth Featuring a Digital Channel-Selection Filter" in IEICE TRANSACTIONS on Electronics,
vol. E87-C, no. 6, pp. 878-887, June 2004, doi: .
Abstract: We have proposed a new low-IF transceiver architecture to simultaneously achieve both a small chip area and good minimum input sensitivity. The distinctive point of the receiver architecture is that we replace the complicated high-order analog filter for channel selection with the combination of a simple low-order analog filter and a sharp digital band-pass filter. We also proposed a high-speed convergence AGC (automatic gain controller) and a demodulation block to realize the proposed digital architecture. For the transceiver, we further reduce the chip area by applying a new form of direct modulation for the VCO. Since conventional VCO direct modulation tends to suffer from variation of the modulation index with frequency, we have developed a new compensation technique that minimizes this variation, and designed the low-phase noise VCO with a new biasing method to achieve large PSRR (power-supply rejection ratio) for oscillation frequency. The test chip was fabricated in 0.35-µm BiCMOS. The chip size was 3
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_6_878/_p
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@ARTICLE{e87-c_6_878,
author={Masaru KOKUBO, Masaaki SHIDA, Takashi OSHIMA, Yoshiyuki SHIBAHARA, Tatsuji MATSUURA, Kazuhiko KAWAI, Takefumi ENDO, Katsumi OSAKI, Hiroki SONODA, Katsumi YAMAMOTO, Masaharu MATSUOKA, Takao KOBAYASHI, Takaaki HEMMI, Junya KUDOH, Hirokazu MIYAGAWA, Hiroto UTSUNOMIYA, Yoshiyuki EZUMI, Kunio TAKAYASU, Jun SUZUKI, Shinya AIZAWA, Mikihiko MOTOKI, Yoshiyuki ABE, Takao KUROSAWA, Satoru OOKAWARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Small-Chip-Area Transceiver IC for Bluetooth Featuring a Digital Channel-Selection Filter},
year={2004},
volume={E87-C},
number={6},
pages={878-887},
abstract={We have proposed a new low-IF transceiver architecture to simultaneously achieve both a small chip area and good minimum input sensitivity. The distinctive point of the receiver architecture is that we replace the complicated high-order analog filter for channel selection with the combination of a simple low-order analog filter and a sharp digital band-pass filter. We also proposed a high-speed convergence AGC (automatic gain controller) and a demodulation block to realize the proposed digital architecture. For the transceiver, we further reduce the chip area by applying a new form of direct modulation for the VCO. Since conventional VCO direct modulation tends to suffer from variation of the modulation index with frequency, we have developed a new compensation technique that minimizes this variation, and designed the low-phase noise VCO with a new biasing method to achieve large PSRR (power-supply rejection ratio) for oscillation frequency. The test chip was fabricated in 0.35-µm BiCMOS. The chip size was 3
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - A Small-Chip-Area Transceiver IC for Bluetooth Featuring a Digital Channel-Selection Filter
T2 - IEICE TRANSACTIONS on Electronics
SP - 878
EP - 887
AU - Masaru KOKUBO
AU - Masaaki SHIDA
AU - Takashi OSHIMA
AU - Yoshiyuki SHIBAHARA
AU - Tatsuji MATSUURA
AU - Kazuhiko KAWAI
AU - Takefumi ENDO
AU - Katsumi OSAKI
AU - Hiroki SONODA
AU - Katsumi YAMAMOTO
AU - Masaharu MATSUOKA
AU - Takao KOBAYASHI
AU - Takaaki HEMMI
AU - Junya KUDOH
AU - Hirokazu MIYAGAWA
AU - Hiroto UTSUNOMIYA
AU - Yoshiyuki EZUMI
AU - Kunio TAKAYASU
AU - Jun SUZUKI
AU - Shinya AIZAWA
AU - Mikihiko MOTOKI
AU - Yoshiyuki ABE
AU - Takao KUROSAWA
AU - Satoru OOKAWARA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2004
AB - We have proposed a new low-IF transceiver architecture to simultaneously achieve both a small chip area and good minimum input sensitivity. The distinctive point of the receiver architecture is that we replace the complicated high-order analog filter for channel selection with the combination of a simple low-order analog filter and a sharp digital band-pass filter. We also proposed a high-speed convergence AGC (automatic gain controller) and a demodulation block to realize the proposed digital architecture. For the transceiver, we further reduce the chip area by applying a new form of direct modulation for the VCO. Since conventional VCO direct modulation tends to suffer from variation of the modulation index with frequency, we have developed a new compensation technique that minimizes this variation, and designed the low-phase noise VCO with a new biasing method to achieve large PSRR (power-supply rejection ratio) for oscillation frequency. The test chip was fabricated in 0.35-µm BiCMOS. The chip size was 3
ER -
English
