All-CMOS radio transceivers and systems-on-a-chip are rapidly making inroads on a wireless market that for years was dominated by bipolar and BiCMOS solutions. It is not a matter of replacing bipolar transistors in known circuit topologies with FETs; the wave of RF-CMOS brings with it new architectures and unprecedented levels of integration. What are its origins? What is the commercial impact? How will RF-CMOS evolve in the future? This paper offers a retrospective and a perspective.

The rapid down-scaling of minimum feature size in CMOS technologies has boosted the RF performance, thereby opening up the RF application area to CMOS. The concurrent reduction of supply voltage pushes the MOSFETs used in circuit design more and more into the moderate-inversion regime of operation. As a consequence, compact MOS models are needed that are accurate in all operating regimes, including the moderate-inversion regime. Advanced analogue applications require accurate modelling of distortion, capacitances and noise. RF application of MOSFETs require the extension of this accurate modelling up to high frequencies and in addition accurate modelling of impedance levels and power gain. The implications for compact MOS models will be discussed, together with the state-of-the-art in compact MOS modelling. Special attention will be paid to some well-known circuit examples, and the compact model requirements needed for a correct description. Where relevant MOS Model 11 will be used to illustrate the discussion.

Application area of mixed signal technology is currently expanded to digital communication, networking, and digital storage systems from conventional digital audio and video systems. Digital consumer electronics are emerged and their markets are extremely increased. Rapid progress of integrated circuit technology has enabled a system level integration on a SoC. Thus mixed signal SoC becomes a majority in LSI industry. Almost all the analog functions should be realized by CMOS technology on SoC, yet some difficulties such as a low transconductance, a large mismatch voltage, and a large 1/f noise should be solved. CMOS device has been considered as a poor device for the analog use, however in reality, it has attained a remarkable progress for analog applications. CMOS device has a variety of circuit techniques to address its own issues and also has an analog performance that increases rapidly with technology scaling. The mixed signal SoC needs a new development strategy and design methodology that covers from system level to device level for addressing tough needs for a shorter development time, a lower cost, and a higher design quality. The optimizations over analog and digital and over system to device must be established for the development success. Difficulty of low voltage operation of further scaled CMOS in analog circuits will be the most serious issue. This results in the saturation of performance and increase of cost. The system level optimization over analog and digital, digital calibration and compensation, and the use of sigma-delta modulation method will give us the solution.

We have proposed a new low-IF transceiver architecture to simultaneously achieve both a small chip area and good minimum input sensitivity. The distinctive point of the receiver architecture is that we replace the complicated high-order analog filter for channel selection with the combination of a simple low-order analog filter and a sharp digital band-pass filter. We also proposed a high-speed convergence AGC (automatic gain controller) and a demodulation block to realize the proposed digital architecture. For the transceiver, we further reduce the chip area by applying a new form of direct modulation for the VCO. Since conventional VCO direct modulation tends to suffer from variation of the modulation index with frequency, we have developed a new compensation technique that minimizes this variation, and designed the low-phase noise VCO with a new biasing method to achieve large PSRR (power-supply rejection ratio) for oscillation frequency. The test chip was fabricated in 0.35-µm BiCMOS. The chip size was 3 3 mm²; this very small area was realized by the advantages of the proposed transceiver architecture. The transceiver also achieved good minimum input sensitivity of -85 dBm and showed interference performance that satisfied the requirements of the Bluetooth standard.

This paper describes a 2.4-GHz downconverter that runs on a 1-V supply. The downconverter integrates an LNA, a quadrature mixer, a complex channel-select band-pass filter (BPF), a limiting amplifier, and a frequency doubler using 0.2-µm CMOS/SOI technology. The frequency doubler doubles the frequency deviation of FM signals as well as the frequency itself, which in turn doubles the modulation index. This improves the sensitivity of FM demodulation. The power consumption of the downconverter is 23 mW with a 1-V power supply. A bit-error-rate (BER) measurement using the downconverter and a demodulation IC shows -76.5-dBm sensitivity at a 0.1% BER.

A 1-V 2.4-GHz-band fully monolithic PLL synthesizer was fabricated in 0.2-µm CMOS/SOI process technology. It includes a voltage-controlled oscillator (VCO) and a 3-GHz fully differential dual-modulus prescaler on a chip. A low-off-leakage-current charge pump is used for open-loop FSK modulation. When the PLL is in the open loop mode, the frequency drift of the output is lower than 2.5 Hz/µsec. The output phase noise is -104 dBc/Hz at 1-MHz offset frequency. The power consumption of the PLL-IC core is 17 mW at 1-V supply voltage. This PLL synthesizer is suitable for a 1-V Bluetooth RF transceiver LSI.

A fully differential direct conversion receiver IC for W-CDMA is presented. The receiver IC consists of an LNA, a quadrature demodulator, low-pass filters (LPFs), and variable gain amplifiers (VGAs). In order to suppress DC offset, which is the most important issue in a direct conversion system, an active harmonic mixer is applied to the quadrature demodulator. Furthermore, a receiving system, including the LNA and an RF filter, adopts a differential architecture to reduce local signal leakage, which generates DC offset. Performance of the entire receiving system was evaluated and DC offset in steady state was measured at only 40 mV. Moreover, DC offset variation at the LNA gain change, which has the largest affect on the receiving performance, was limited to 70 mV, which is less than -10 dB compared to desired signal strength. It was confirmed by computer simulation that the DC offset variation at the LNA gain change did not degrade bit error rate (BER) performance at all.

A linear-in-dB gain-control amplifier for direct conversion systems employs linearized transconductors in a core amp, a dc offset canceler, and a gain control circuit. The offset compensation circuit achieves a constant corner frequency over a gain range of 14 to 76 dB by simultaneous tuning of the transconductors.

This paper proposes a new configuration of the Doherty amplifier by introducing digital signal processing that realizes a high efficiency over a wide range of output power. The configuration includes two branches; one branch has a class AB amplifier as the carrier amplifier and the other has two class B amplifiers in cascade as the peak amplifier. Each branch is directly controlled by the digital signal processing unit. The unit controls input power allocation to each branch by a method derived from equations characterizing the carrier and the peak constituent amplifiers. The method includes the compensation of the amplifier for degradation due to nonlinearities. The output power of each constituent amplifier is adjusted by drain DC biases. Calculated characteristics agree well with those obtained by the measurement of a fabricated proposed amplifier, whose efficiency is higher than that of the conventional class AB power amplifiers. Furthermore, a simulation for the OFDM signal specified by the radio LAN shows that the amplifier has sufficient linearity, and that the efficiency exceeds 20% at the output of 20 dBm.

Design approach to improving f_max of InP-based HBTs by combining lateral scaling (lithographic scaling) and vertical scaling (improving f_T) is discussed. An HBT scaling model is formulated to provide means of analyzing the essential impact of scaling on f_max. The model was compared with measurements of single and double heterojunction bipolar transistors with different f_T and various emitter sizes. While a high f_max of 313 GHz was achieved using submicron HBT with high f_T, it was found that further improvement could have been obtained by reducing the emitter resistance, which has imposed considerable limit on lateral scaling.

Gate-to-bulk overlap capacitance (CGBO) cannot be ignored for long gate channel MOSFET's that are used for various I/O and analog circuits. We present a simple and yet accurate CGBO measurement and extractions by using a group of MOSFET's. Dedicated test structures using 0.18 µm shallow trench isolation technology were fabricated for the purpose. The effect of CGBO has been successfully analyzed. Validity of the CGBO extraction has been verified by comparing measured time delay of 51 stage ring oscillators with simulated data using our customized UCB SPICE3 simulator.

This paper presents a methodology for optimizing the layout of on-chip spiral inductors using structural parameters and design frequency in a response surface method. The proposed method uses scattering parameters (S-parameter) to express inductor characteristics, and hence is independent of spiral geometries and equivalent circuit models. The procedure of inductor optimization is described, and a design example is presented.

The present paper proposes differential transmission line structures on Si ULSI. Interconnect structures are examined using numerical results from a two-dimensional electromagnetic simulation (Ansoft, 2D Extractor). The co-planar and diagonal-pair lines are found to have superior characteristics for gigahertz signal propagation through long interconnects. The proposed diagonal-pair line can reduce the crosstalk noise and interconnect resource concurrently.

This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15 µm-CMOS process. The total chip area of the PLL is reduced to 1/2 of the previous one. The jitter performance is almost equal to conventionally biased PLL.

An adaptive 4-state phase-frequency detector (PFD) for clock and data recovery (CDR) PLL of non return to zero (NRZ) data is presented. The PLL achieves false-lock free operation with rapid frequency-capture and wide bit-rate-capture range. The variable bit rate operation is achieved by adaptive delay control of data delay. Circuitry and overall architecture are described in detail. A z-Domain analysis is also presented.

This paper presents a novel class of sigma-delta modulator topologies for low-voltage, high-speed, and high-resolution applications with low oversampling ratios (OSRs). The main specifications of these architectures are the reduced analog circuit requirements, large out-of-band gain in the noise transfer function (NTF) without any stability concerns to achieve high signal to noise ratio (SNR) with a low OSR, and unity-gain signal transfer function (STF) to reduce the harmonic distortions resulted from the analog circuit imperfections. To demonstrate the efficiency of the proposed modulator architectures a prototype with HSPICE is implemented. A low-power two-stage class A/AB OTA with modified common mode feedback (CMFB) circuit in the first stage is used to implement the fourth order modulator. Simulation results with OSR of 16 give signal to noise plus distortion ratio (SNDR) and dynamic range (DR) of 90-dB and 92.5-dB including the circuit noise in the 1.25-MHz signal bandwidth, respectively. The circuit is implemented in a 0.13-µm standard CMOS technology. It dissipates about 40-mW from a single 1.2-V power supply voltage.

Dynamic non-linearities are of more importance in highly-linear high-speed applications such as software radios. In this paper, a fully-analytical approach to estimate the statistics of dynamic non-linearity parameters of pipeline analog-to-digital converters (ADCs) in the presence of circuit non-idealities is presented. These imperfections include the capacitor mismatches and the non-idealities in the operational amplifiers (op-amps). The most two important ADC dynamic non-linearity parameters, the spurious-free dynamic range (SFDR) and the signal-to-noise-and-distortion ratio (SNDR) are quantified here and closed-form formulas are presented. These formulas are useful for design automation as well as hand calculations of highly-linear pipeline ADCs. Behavioral simulations are presented to show the accuracy of the proposed equations.

This paper presents the improvement of the transient response and stability for a two-stage DC-DC converter by removing the output inductor. The conventional two-stage converter consists of a buck converter used as the first stage and a half-bridge converter used as the second stage. The proposed circuit topology removing the output inductor and the conventional topology are compared. Removing the output inductor results in the system-order reduction of the transfer function. As a result, the stability is improved, and the crossover frequency of the open-loop transfer function becomes higher. The effectiveness of the proposed circuit topology was experimentally confirmed.

We propose a novel mobility reduction cancellation technique for an OTA (Operational Transconductance Amplifier). The proposed technique can be easily realized by using conventional OTAs. The proposed OTAs have good linearity. The simulation results show that the THD is less than 1% for 1.8 Vp-p at 3 V supply voltage.

We propose a neural-sensing LSI with a bi-directional wireless interface, which is capable of detecting 5-channel neural signals in a living animal. The proposed sensing LSI consists of a multiplexer with 5-channels selectable from 10 channels, a chopper amplifier using a new direct-chopper-input scheme, a programmable multi-mode analog-to-digital converter (ADC), and a wireless-transmitter/receiver with BPSK modulation signals. The test-chip was implemented by mixed-signal 0.35-µm CMOS technology. We measured the test chip and confirmed basic operations of these blocks. The chopper-amplifier achieved 66-dB DC gain, bandwidth of 400 kHz, and 4-µV noise with power dissipation of 6-mW with a 3-V supply. We observed real nerve signals in a living cricket using the proposed chopper amplifier. ADC achieved 52-ksps operation with power dissipation of 0.43-mW at 3-V supply. The wireless transmitter achieved 1-Mbps data transmission at a distance of 1-m with 1.5-mW power dissipation at 3-V supply.

A low supply voltage CMOS variable-gain low noise amplifier (LNA) is presented in this paper. A folded cascode structure is used to reduce the supply voltage to only 1 V. The conversion gain of the LNA can be controlled by the bias voltage of the connon-gate transistor. When the input signal is weak, the circuit works at high-gain mode to improve the sensitivity. Otherwise, when the input signal is strong, the circuit works at low-gain mode to increase the linearity.

A current folded mixer achieving low 1/f noise for low power direct conversion receivers is proposed. The proposed mixer topology decouples the design tradeoffs between noise figure, conversion gain and third order intermodulation distortion. Comparisons with the conventional current-reuse injection topology, the current folded mixer with 1/f noise minimized shows significant improvements. Experimental design on 2.4-GHz band and with 0.18-µm CMOS technology has revealed the advantages of the newly proposed topology.

We have developed a V-band monolithic HEMT amplifier with single positive power supply. The amplifier used two types of RF grounds for coplanar waveguides (CPW) as transmission lines. One RF ground has a voltage of 0 V at DC, and the other RF ground has a voltage of more than 0 V at DC. A prototype of the monolithic amplifier was fabricated. The amplifier had a gain of 21.0 dB, a Rollett stability factor K of 2.35, an input VSWR of 1.82, and an output VSWR of 2.14 at 59.5 GHz.

The threshold voltage mismatch of FD (Fully depleted) SOI (Silicon on insulator) devices have been studied. Floating body MOSFETs operating at high drain voltage show a large mismatch in the threshold voltage compared with body-tied MOSFETs. Those experimental data under different drain voltages indicate that both floating body effect and DIBL (Drain induced barrier lowering) are involved in the threshold voltage mismatch of floating body MOSFETs.

This paper analyzes the input-dependent sample-time error in MOS sampling circuits caused by the finite slope of the sampling clock, and clarifies the following: (i) Input-dependent sampling jitter causes phase modulation in the sampled data. (ii) The formulas for SDR due to such sampling errors are explicitly derived. (iii) NMOS sampling circuits generate even-order harmonics, which are greatly reduced by using a differential topology. (iv) CMOS sampling circuits without clock skew between V_clk and generate odd-order harmonics which a differential topology cannot help cancel, whereas circuits with clock skew generate even-order as well as odd-order harmonics. (v) For single-ended sampling circuits, the SDR of CMOS circuits without clock skew is better than that of NMOS circuits. (vi) NMOS differential sampling circuits are relatively insensitive to input-dependent sampling-time error effects, which would be the best regarding to the input-dependent sampling-time error effects. (vii) Its effects in case of NMOS differential samplers with finite skew between plus and minus path clocks are discussed. (viii) Its effects in CMOS samplers with finite skew between PMOS and NMOS clocks are discussed.

A high-speed bipolar ECL comparator circuit with a latch is described. The spike noise generated by charging the base-to-emitter diffusion capacitor on the transition of differential transistors' switching in a sample-and-latch circuit is reduced by inserting the emitter degeneration resistors so that neither of them becomes completely cut off. The frequency bandwidth of a pre-amplifier is increased by using coupled inductors as differential loads. As a result, -3 dB frequency bandwidth of a pre-amplifier becomes 10 GHz, and 4 GS/s operation with 6-bit equivalent precision from a 3.3 V power supply is confirmed by the circuit simulation using device parameters from the 25 GHz silicon bipolar process.

A Switched-Opamp is a device in SC circuits for replacing switches with Opamps which operate like a switch. This technique can be acheived in very low voltage operation. In this paper, we present a design for a Switched-Opamp that can operate at a low supply voltage during the ON-phase and can maintain a high output impedance during the OFF-phase.

A CMOS voltage-to-current converter in weak inversion is presented in this Letter. It can operate for low supply voltage and its power consumption is also low. As the input voltage varies from -0.15 V to 0.15 V, the measured maximum linearity error for the proposed voltage-to-current converter, is about 3.35%. Its power consumption is only 26 µW under the supply voltage of 2 V. The proposed voltage-to-current converter has been fabricated in a 0.5 µm N-well CMOS 2P2M process. The proposed circuit is expected to be useful in analog signal processing applications.

A compact low-voltage CMOS exponential current-to-voltage converter free from transconductance parameter matching between NMOS and PMOS is proposed. The circuit is composed of level shift circuits and current mirrors. The SPICE simulation results show a 27 dB linear range with a linearity error of less than 1 dB.

This letter proposes an output driver which reduces simultaneous switching noise without degradation of rise/fall time. At the start of transition period, the driver optimally uses both VDD and VSS current by switching of on-chip bypass capacitors. The proposed driver achieves 27-percent reduction in peak current with faster transition time.

This article presents the CMOS transimpedance amplifier (TIA) for gigabits optical communication, where an analytical method for designing a wideband TIA using different inductive peaking technology is introduced. In this study, we derive and analyze the transfer function (V_out/I_in) of the TIA circuit from the equivalent circuit model. By adding the peaking inductor in different locations, the TIA 3-dB bandwidth can be enhanced without sacrificing the transimpedance gain. These TIA designs have been realized by the advanced CMOS process, and the measured results confirm the predictions from the analytic approach, where the inductive peaking is an useful way to enhance the TIA bandwidth.

A fully integrated RF front-end for W-CDMA applications including a low noise amplifier, a down conversion mixer, a digitally programmable gain amplifier, an on-chip VCO, and a fractional-N frequency synthesizer is designed using a 0.35-µm CMOS process. A multi-stage ring shaped on-chip LC-VCO exhibiting bandpass characteristics overcomes the limitation of low-Q components in the tank circuits and improves the phase noise performance. The measured phase noise of the on-chip VCO is -134 dBc/Hz at 1 MHz offset. The receiver RF front-end achieves a NF of 3.5 dB, an IIP3 of -16 dBm, and a maximum gain of 80 dB. The receiver consumes 52 mA with a 3-V supply and occupies only 2 mm² die area with minimal external components.

Novel designs of multiple-valued logic (quaternary) half adder, full adder, and carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus, no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries is half compared to binary ones and the propagation delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with large number of bits.

This paper presents the realization of the radio frequency (RF) power and data transmission for implantable microstimulators. This implantable device composes an internal RF front-end circuit, a control circuit, and a microstimulator. A 2 MHz AM-modulated signal including the power and data necessary for the implantable device is received, and a stable dc voltage and digital data will be extracted to further stimulate neuromuscular stimulation. In this implantable stimulator, the digital part is implemented by field programmable gate array (FPGA), and the analog part is implemented in a standard single-poly fifth-metal 0.25 µm CMOS process. The latter occupies a silicon area smaller than 0.00638 mm² and produces an output current with 5-bit resolution for stimulations. The measuring stimulating current is 2.77 mA while the stimulation frequency is from 20 Hz to 2 kHz and the pulse width of stimulation current is from 100 µs to 450 µs. In addition, the simulation results of the RF front-end circuit and the verification of the control logic circuit are also presented in this paper.

This paper presents a new high-speed and area-efficient dual-rail PLA. The proposed circuit includes three schemes: 1) a divided column scheme (DCS), 2) a programmable sense-amplifier activation scheme (PSAS), and 3) an interdigitated column scheme (ICS). In the DCS, a column circuit of a PLA is divided and each circuit operates in parallel. This enhances the performance of the PLA, and this scheme becomes more effective as input data bandwidth increases. The PSAS is used to generate an activation pulse for sense amplifiers in the PLA. In this scheme, the proposed delay generators enable to minimize a timing margin depending on process variations and operating conditions. The ICS is used to enhance the area-efficiency of the PLA, where a method of physical compaction is employed. This scheme is effective for circuits which have the regularity in logic function such as arithmetic circuits. As applications of the proposed PLA, a comparator, a priority encoder, and an incrementor for 128-bit data processing were designed. The proposed circuit design schemes achieved a 22.2% delay reduction and a 37.5% area reduction on average over the conventional high-speed and low-power PLA in a 0.13-µm CMOS technology with a supply voltage of 1.2 V.

Integral equation method is used to compute three-dimension-structure capacitance in this paper. Since some multi-conductor structures present regular periodic property, the periodic cell is used to reduce the computational domain with adding appropriate magnetic and electric walls. The periodic Green's function in the integral equation method is represented in the form of infinite series with slow convergence. In this paper, Shanks transformation is used to accelerate the convergence. Numerical examples show that the proposed method is accurate with a much higher efficiency in capacitance extraction for 3-D periodic structures.

In this study, an improved heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) active mixer is designed and fabricated. The HBT MMIC active mixer that is integrated with a low-noise amplifier (LNA) and active power adder can not only achieve high isolation, but can also dispense with one active component and reduce power consumption at the same time. Measurement results show that the conversion gain, LO-RF isolation, and double sideband noise figure (DSB-NF) of the proposed mixer are 22 dB, 40 dB, and 7 dB, respectively.

The proposed comparator includes high gain preamplifier with a new swing limiter. It is shown that, for a given unity gain bandwidth, the high gain preamplifier of high output impedance can be made faster than the low gain one if properly combined with a high-speed low-level swing limiter.