A low-voltage silicon-on-insulator (SOI) voltage-reference circuit has been developed. It is based on threshold-voltage-summation architecture and the output is not affected by the input offset of the feedback amplifier. Thus, the output dispersion is considerably reduced. An undoped MOSFET is used as a depletion-mode transistor because of its small threshold voltage. The temperature dependence of normal and undoped MOSFETs in fully depleted CMOS/SOI technology is studied for designing a temperature-insensitive voltage-reference circuit. A prototype circuit, fabricated on a fully depleted CMOS/SIMOX process, has a measured reference voltage of 530 16.8 mV (3σ), and can operate at a supply voltage as low as 0.6 V. The measured temperature coefficient is 0.02 0.06 mV/ (3σ).

The performance of radio frequency integrated circuits (RFICs) in silicon-on-insulator (SOI) technology can be improved by using a high-resistivity SOI substrate. We investigated the correlation between substrate resistivity and the performance of a low noise amplifier (LNA) on ELTRAN(R) SOI-Epi wafersTM, whose resistivity can be controlled precisely. The use of high-resistivity ELTRAN wafers improves the Q-factor of spiral inductors, and thereby increases the gain and narrows the bandwidth of the LNA. Using the high-resistivity ELTRAN wafers, we have successfully fabricated a 2.4-GHz and 5-GHz CMOS LNA in 0.35-µm SOI CMOS technology, whose process cost is lower than the latest CMOS technologies.

A new low-power feedback structure for a power amplifier (PA) reduces signal distortion while keeping the power efficiency of the PA high. The feedback structure injects the envelope of the third-order harmonics into the input signal. In adopting this method for a class-A amplifier, we obtain over 10% higher efficiency while maintaining the same adjacent channel power ratio (ACPR). The power consumption of additional circuit is 200 µW.

This paper proposes a novel access control scheme with collision detection that utilizes multiple-input multiple-output (MIMO) technology. Carrier sense multiple access with collision detection (CSMA/CD) is used in Ethernet wired local area networks (LANs) for media access control (MAC). CSMA/CD can immediately abort a transmission if any collision is detected and is thus able to change to a retransmission state. In Ethernet, CSMA/CD results in a transmission efficiency of approximately 90% because the protocol makes the transmission band available for useful communication by this retransmission function. Conversely, in conventional wireless LANs (WLANs), the packet collisions due to interfering signals and the retransmission due to collisions are significant issues. Because conventional WLANs cannot detect packet collisions during signal transmission, the success of a transmission can only be determined by whether an acknowledgment (ACK) frame has been received. Consequently, the transmission efficiency is low — approximately 60%. The objective of our study is to increase the transmission efficiency of WLANs to make it at least equal to that of Ethernet. Thus, we propose a novel access control scheme with collision detection that utilizes MIMO technology. When preamble signals are transmitted before transmitting data packets from an antenna, the proposed scheme can detect packet collisions during signal transmission at another antenna; then, the affected packets are retransmitted immediately. Two fundamental technologies are utilized to realize our proposed scheme. The first technology is the access control protocol in the MAC layer in the form of the MIMO frame sequence protocol, which is used to detect signal interference. The other technology is signal processing in the physical (PHY) layer that actualizes collision detection. This paper primarily deals with the proposed MAC layer scheme, which is evaluated by theoretical analyses and computer simulations. Evaluation by computer simulations indicate that the proposed scheme in a transmission efficiency of over 90%.

To reduce power consumption of wireless terminals, we have developed ultra-low leakage regulator circuits that control the intermittent terminal operation with very small activity ratio. The regulator circuits supply about 100 mA in the active mode and cut the leakage current to a nanoampere level in the standby mode. The operation of the ultralow-leakage regulator circuits with CMOS/SOI and bulk technologies is described. The leakage-current reduction mechanism in a proposed power switch with bulk technology is explained. Measurement shows that the power switch using reversely biased bulk transistors has a leakage current that is almost as small as that of conventional CMOS/SOI transistor switches.

A high-image-rejection wireless receiver with an N-phase active RC complex filter is proposed and analyzed. Signal analysis shows that the double-conversion receiver with (N+N2) mixers corrects the gain and phase mismatches of the adjacent image. Monte Carlo simulations evaluate the relation between image-rejection performances and the dispersions of device parameters for the double-conversion wireless receiver. The Monte Carlo simulations show that the image rejection ratio of the adjacent image depends almost only on R and C mismatches in the complex filter.

Quadrature voltage-controlled oscillators (VCOs) with current-weight-average and voltage-weight-average phase-adjusting architectures are studied. The phase adjusting equalizes the oscillation frequency to the LC-resonant frequency. The merits of the equalization are explained by using Leeson's phase noise equation and the impulse sensitivity function (ISF). Quadrature VCOs with the phase-adjusting architectures are fabricated using 180-nm TSMC CMOS and show low-phase-noise performances compared to a conventional differential VCO. The ISF analysis and small-signal analysis also show that the drawbacks of the current-weight-average phase-adjusting and voltage-weight-average phase-adjusting architectures are current-source noise effect and large additional capacitance, respectively. A voltage-average-adjusting circuit with a source follower at its input alleviates the capacitance increase.

A fifth-order switched-capacitor (SC) complex filter was implemented in 0.2-µm CMOS technology. A novel SC integrator was developed to reduce the die size and current consumption of the filter. The filter is centered at 24.730.15 kHz (3δ) and has a bandwidth of 20.260.3 kHz (3δ). The image channel is attenuated by more than 42.6 dB. The in-band third-order harmonic input intercept point (IIP3) is 17.3 dBm, and the input referred RMS noise is 34.3 µVrms. The complex filter consumes 350 µA with a 2.0-V power supply. The die size is 0.578 mm2. Owing to the new SC integrator, the filter achieves a 27% reduction in die size without any degradation in its characteristics, including its noise performance, compared with the conventional equivalent.

A micro-power active-RFID LSI with an all-digital RF-transmitting scheme achieves experimental 10-m-distance communication with a 1-Mbps data rate in the 300-MHz frequency band. The IC consists of an RF transmitter and a power supply circuit. The RF transmitter generates wireless signals without a crystal. The power supply circuit controls the energy flow from the battery to the IC and offers intermittent operation of the RF transmitter. The IC draws 1.6 µA from a 3.4-V supply and is implemented in a 0.2-µm CMOS process in an area of 1 mm2. The estimated lifetime of the IC is over ten years with a coin-size battery.

A 1-V 2-GHz receiver that exhibits an image rejection of 49 dB is described. It consists of a low-noise amplifier, a quadrature mixer and on-chip polyphase filters, and was fabricated by 0.2-µm fully depleted CMOS/SIMOX technology. The quadrature mixer employs an LC-tuned folded structure with a common RF input for I and Q channels. This enables 1-V operation, suppresses phase errors in LO signals, and improves the image-rejection performance by about 15-dB compared to a conventional quadrature architecture. The current source of the single-to-balance converter at the mixer input consists of a transistor and an LC tank in a cascode configuration. This enhances its output impedance and improves its common-mode-rejection ratio (CMRR) and the IIP2 characteristics of the receiver. The chip consumes 12 mW with 1-V power supply. The receiver provides an NF of 10 dB with an IIP3 of -15.8 dBm and IIP2 of 12.3 dBm.

This paper describes a 2.4-GHz downconverter that runs on a 1-V supply. The downconverter integrates an LNA, a quadrature mixer, a complex channel-select band-pass filter (BPF), a limiting amplifier, and a frequency doubler using 0.2-µm CMOS/SOI technology. The frequency doubler doubles the frequency deviation of FM signals as well as the frequency itself, which in turn doubles the modulation index. This improves the sensitivity of FM demodulation. The power consumption of the downconverter is 23 mW with a 1-V power supply. A bit-error-rate (BER) measurement using the downconverter and a demodulation IC shows -76.5-dBm sensitivity at a 0.1% BER.

A 1-V 2.4-GHz-band fully monolithic PLL synthesizer was fabricated in 0.2-µm CMOS/SOI process technology. It includes a voltage-controlled oscillator (VCO) and a 3-GHz fully differential dual-modulus prescaler on a chip. A low-off-leakage-current charge pump is used for open-loop FSK modulation. When the PLL is in the open loop mode, the frequency drift of the output is lower than 2.5 Hz/µsec. The output phase noise is -104 dBc/Hz at 1-MHz offset frequency. The power consumption of the PLL-IC core is 17 mW at 1-V supply voltage. This PLL synthesizer is suitable for a 1-V Bluetooth RF transceiver LSI.

The design and performance of a sub-nanoampere two-stage power management circuit that uses off-chip capacitors for energy accumulation are presented. Focusing on the leakage current and the transition time of the power switch transistor, we estimated the minimum current for accumulating. On the basis of the results, we devised a two-stage power management architecture for sub-nanoampere operation. The simulated and experimental results for the power management circuit describe the accumulating operation with a 1-nA current source.

To reduce the power dissipation of the receiver in accordance with the intensity of the received signal, we developed the first intra-symbol intermittent (ISI) radio-frequency (RF) front end with 0.35-µm CMOS technology. In the demodulation mechanism, the RF output of the low-noise amplifier (LNA) is down-converted to an intermediate frequency (IF) by the mixer, and the LNA and mixer operate synchronously and intermittently within the length of a single symbol. Because the time-averaged power consumption is proportional to the operating time, the demodulation can be performed with low power by making the total operating time short. We experimentally demonstrate that demodulation (BPSK: 9.6 kbps) is properly achieved with the operating-time ratio of 12%. This ISI operation of the RF front end is enabled by a newly devised fast-transition LNA and mixer. A theoretical analysis of aliasing noise reveals that RF ISI operation is more useful than current-control with continuous operation and that an operating-time ratio of 10% is optimal.

This paper dicusses the emitter-resistance (RE) effect on the cutoff frequency (fT) of silicon heteroemitter bipolar transistors (Si HBTs) by using two-dimensional device simulation, circuit simulation and small-signal analysis. It is shown that an approximate formula fT=fT0/(1+2πfT0RECC) agrees well with the device and circuit simulation results. The emitter resistance affects the cutoff frequency greatly. The conductance modulation in lightly-doped heteroemitter layers with a heavily-doped backup layer is also analyzed. It is found that the carrier injection from the heavily-doped backup layer into the lightly-doped heteroemitter layer reduces the emitter resistance to one-fourth the value at best. The permissible lower limit of electron mobility in heteroemitter is estimated roughly to be 2 cm2v-1s-1.