1-2hit |
Kiyofumi SAKAGUCHI Nobuhiko SATO Kenji YAMAGATA Tadashi ATOJI Yasutomo FUJIYAMA Jun NAKAYAMA Takao YONEHARA
The quality of ELTRAN wafers has been improved by pre-injection in epitaxial growth, surface treatment just before bonding, high temperature annealing at bonding, high selective etching and hydrogen annealing. The pre-injection reduces defects. The surface treatment eliminates edge-voids. The high temperature bonding dramatically reduces voids all over the wafer. Hydrogen annealing is very effective for surface flattening and boron out-diffusion. In particular, the edge-void elimination by the surface treatment just before bonding is greatly effective for enlarging the SOI area and reduces the edge exclusion down to only two mm. The gate oxide integrity is well evaluated. This process promises high yield and through-put, because each of the steps can be independently optimized.
Junichi KODATE Mamoru UGAJIN Tsuneo TSUKAHARA Takakuni DOUSEKI Nobuhiko SATO Takehito OKABE Kazuaki OHMI Takao YONEHARA
The performance of radio frequency integrated circuits (RFICs) in silicon-on-insulator (SOI) technology can be improved by using a high-resistivity SOI substrate. We investigated the correlation between substrate resistivity and the performance of a low noise amplifier (LNA) on ELTRAN(R) SOI-Epi wafersTM, whose resistivity can be controlled precisely. The use of high-resistivity ELTRAN wafers improves the Q-factor of spiral inductors, and thereby increases the gain and narrows the bandwidth of the LNA. Using the high-resistivity ELTRAN wafers, we have successfully fabricated a 2.4-GHz and 5-GHz CMOS LNA in 0.35-µm SOI CMOS technology, whose process cost is lower than the latest CMOS technologies.