A modified 0.35 µm gate-length MOSFET large-signal microwave device model, based on the widely used BSIM3 model, is presented in this report. This large-signal microwave model includes a BSIM3 model together with the passive components required to fit the device dc and microwave characteristics over a wide range of biasing points and frequency operation. In this report, we propose a methodology to improve the device microwave linearity by controlling a suitable biasing condition, which is based on the predictions of this modified CMOS large-signal model. The input IM3 enhances more than 10 dB at a 2.4 GHz operation. Furthermore, the adjacent channel power ratio also improves 7.5 dB with proper choosing device dc bias.

Vertical Power MOSFETs are widely designed by deep well structures for breakdown requirement. In this study, we proposed, simulated, and analyzed a "shallow dual well" structure Power MOSFET, which utilize an n-well to cover the conventional p-well. The cell pitch can be reduced and results in an increased cell density. The reduced cell pitch and increased cell density improves the gate charge and on resistance performances about 66.5% and 15.8% without sacrificing the device breakdown owing to a shallow junction design. In addition, with the dual well structure design, the breakdown point will occur at the center of the well. Therefore, the capability of avalanche energy can be improved about 1.9 times than the tradition well structure.

A high quality-factor of active inductor has been implemented by using the 0.18 µm 1P6M CMOS technologies in this work. By adding a feedback resistance and a regulated gain stage transistor into the conventional cascade-grounded approach, the quality-factor and performance of CMOS active inductor can be improved. This novel active inductor demonstrated a maximum quality-factor of 540 and a 3.2 nH inductance at 4.3 GHz, where the self-resonant frequency was 5.4 GHz. An active CMOS bandpass filter was also fabricated including this tunable high quality factor active inductor, performing an insertion loss of 0.2 dB and a return loss more than 32 dB with a tuning range from 3.45 GHz to 3.6 GHz. The input IP3 was -2.4 dBm, and the noise figure was 14.1 dB with a 28 mW dc power consumption.

This article presents the CMOS transimpedance amplifier (TIA) for gigabits optical communication, where an analytical method for designing a wideband TIA using different inductive peaking technology is introduced. In this study, we derive and analyze the transfer function (Vout/Iin) of the TIA circuit from the equivalent circuit model. By adding the peaking inductor in different locations, the TIA 3-dB bandwidth can be enhanced without sacrificing the transimpedance gain. These TIA designs have been realized by the advanced CMOS process, and the measured results confirm the predictions from the analytic approach, where the inductive peaking is an useful way to enhance the TIA bandwidth.

A high barrier Schottky gate on InGaP/InGaAs doped-channel FETs (DCFETs) provides a high current density, high gate-to-drain breakdown voltage and a better linear operation over a wide gate bias range. However, these doped-channel devices are limited by a large parasitic resistance associated with a 20 nm thick undoped InGaP layer beneath the gate metal. In this study, we inserted a Si δ-doped layer inside this high bandgap undoped InGaP layer to reduce parasitic resistances and to enhance device DC and RF power performance. These modified DCFETs (M-DCFETs) demonstrated an output power density of 204 mW/mm, a power-added efficiency of 45%, and a linear power gain of 18.3 dB for an 1 mm gate-width device under a 2.4 GHz operation. These characteristics suggest that doped-channel FETs with a Si δ-doped layer provide a good potential for high power microwave device applications.

Devices DC, RF, and microwave power performances between Al0.3Ga0.7As/In0.15Ga0.85As double doped-channel FET (D-DCFETs), conventional doped-channel FETs (DCFETs) and HEMTs are compared with each other. Device linearity and power performance have been improved by a double doped-channel design. The D-DCFETs provides a higher current density, higher gate breakdown voltage, and improves gate operation bias range as well as frequency performance. The linear power gain and output power for D-DCFETs is 19 dB and 305 mW/mm with a power-added efficiency of 52% at Vds = 2.5 V under a 1.9 GHz operation. These advantages suggest that double doped-channel design is more suitable for a high linearity and high microwave power device applications.