A fully integrated RF front-end for W-CDMA applications including a low noise amplifier, a down conversion mixer, a digitally programmable gain amplifier, an on-chip VCO, and a fractional-N frequency synthesizer is designed using a 0.35-µm CMOS process. A multi-stage ring shaped on-chip LC-VCO exhibiting bandpass characteristics overcomes the limitation of low-Q components in the tank circuits and improves the phase noise performance. The measured phase noise of the on-chip VCO is -134 dBc/Hz at 1 MHz offset. The receiver RF front-end achieves a NF of 3.5 dB, an IIP3 of -16 dBm, and a maximum gain of 80 dB. The receiver consumes 52 mA with a 3-V supply and occupies only 2 mm2 die area with minimal external components.

This letter describes an efficient architecture for a Software Defined Radio (SDR) Wideband Code Division Multiple Access (WCDMA) receiver using for high performance wireless communication systems. The architecture is composed of a Radio Frequency (RF) front-end, an Analog-to-Digital Converter (ADC), and a Quadrature Amplitude Modulation (QAM) demodulator. A coherent demodulator, with a complete digital synchronization scheme, achieves the bit-error rate (BER) of 10-6 with the implementation loss of 0.5 dB for a raw Quadrature Phase Shift King (QPSK) signal.

Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth is preferred to being adjusted accordingly. In this paper, a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement. This algorithm, based on the recursive least squares (RLS) criterion, suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithm can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drivers that require a short initial preamble period.

This paper describes the design of a programmable QAM transceiver for VDSL applications. A 12-b DAC with 64-dB spurious-free dynamic range (SFDR) at 75-MS/s and an 11-b ADC with 72.3-dB SFDR at 70-MS/s are integrated in this complete physical layer IC. A digital IIR notch filter is included in order to not interrupt existing amateur radio bands. The proposed dual loop AGC adjusts the gain of a variable gain amplifier (VGA) to obtain maximum SNR while avoiding saturation. Using several low power techniques, the total power consumption is reduced to 300-mW at 1.8-V core and 3.3-V I/O supplies. The transceiver is fabricated in a 0.18-µm CMOS process and the chip size is 5-mm 5-mm. This VDSL transceiver supports 13-Mbps data rate over a 9000-ft channel with a BER < 10-7.

This paper describes a technique for background digital multistage calibration in the removal of nonlinearities caused by design limitations in pipelined analog-to-digital converters (ADCs). Foreground initialization reduces the calibration time. Furthermore, an improved background skip-and-fill method enables the ADC to trace environmental changes. This method uses a least mean square adaptive algorithm that is digitally implemented with a significantly reduced number of tap coefficients.

This work describes a 2.4 GHz frequency synthesizer based on a delay-locked loop (DLL). Because the proposed frequency synthesizer is basically developed from a DLL, it has no jitter accumulation thereby resulting in a low close-in phase noise of -105 dBc/Hz. Although only 9 delay cells are used, the proposed delay cell reusing scheme realizes frequency multiplication factors greater than 240 and provides multiple frequency output with the resolution of phase detector (PD) comparison frequency. This architecture has been verified by implementing the synthesizer in a 0.18 µm CMOS technology.

A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.

This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications, Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.