This letter describes an efficient architecture for a Software Defined Radio (SDR) Wideband Code Division Multiple Access (WCDMA) receiver using for high performance wireless communication systems. The architecture is composed of a Radio Frequency (RF) front-end, an Analog-to-Digital Converter (ADC), and a Quadrature Amplitude Modulation (QAM) demodulator. A coherent demodulator, with a complete digital synchronization scheme, achieves the bit-error rate (BER) of 10-6 with the implementation loss of 0.5 dB for a raw Quadrature Phase Shift King (QPSK) signal.

This paper describes the design of a programmable QAM transceiver for VDSL applications. A 12-b DAC with 64-dB spurious-free dynamic range (SFDR) at 75-MS/s and an 11-b ADC with 72.3-dB SFDR at 70-MS/s are integrated in this complete physical layer IC. A digital IIR notch filter is included in order to not interrupt existing amateur radio bands. The proposed dual loop AGC adjusts the gain of a variable gain amplifier (VGA) to obtain maximum SNR while avoiding saturation. Using several low power techniques, the total power consumption is reduced to 300-mW at 1.8-V core and 3.3-V I/O supplies. The transceiver is fabricated in a 0.18-µm CMOS process and the chip size is 5-mm 5-mm. This VDSL transceiver supports 13-Mbps data rate over a 9000-ft channel with a BER < 10-7.

This paper describes a technique for background digital multistage calibration in the removal of nonlinearities caused by design limitations in pipelined analog-to-digital converters (ADCs). Foreground initialization reduces the calibration time. Furthermore, an improved background skip-and-fill method enables the ADC to trace environmental changes. This method uses a least mean square adaptive algorithm that is digitally implemented with a significantly reduced number of tap coefficients.