A 300-mW Programmable QAM Transceiver for VDSL Applications

Hyoungsik NAM; Tae Hun KIM; Yongchul SONG; Jae Hoon SHIM; Beomsup KIM; Yong Hoon LEE

A 300-mW Programmable QAM Transceiver for VDSL Applications

Hyoungsik NAM, Tae Hun KIM, Yongchul SONG, Jae Hoon SHIM, Beomsup KIM, Yong Hoon LEE

Full Text Views

0

Cite this

Summary :

This paper describes the design of a programmable QAM transceiver for VDSL applications. A 12-b DAC with 64-dB spurious-free dynamic range (SFDR) at 75-MS/s and an 11-b ADC with 72.3-dB SFDR at 70-MS/s are integrated in this complete physical layer IC. A digital IIR notch filter is included in order to not interrupt existing amateur radio bands. The proposed dual loop AGC adjusts the gain of a variable gain amplifier (VGA) to obtain maximum SNR while avoiding saturation. Using several low power techniques, the total power consumption is reduced to 300-mW at 1.8-V core and 3.3-V I/O supplies. The transceiver is fabricated in a 0.18-µm CMOS process and the chip size is 5-mm 5-mm. This VDSL transceiver supports 13-Mbps data rate over a 9000-ft channel with a BER < 10^-7.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.8 pp.1367-1375

Publication Date: 2004/08/01

Publicized

Online ISSN

DOI

Type of Manuscript: PAPER

Category: Microwaves, Millimeter-Waves

Cite this

Copy

Hyoungsik NAM, Tae Hun KIM, Yongchul SONG, Jae Hoon SHIM, Beomsup KIM, Yong Hoon LEE, "A 300-mW Programmable QAM Transceiver for VDSL Applications" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 8, pp. 1367-1375, August 2004, doi: .
Abstract: This paper describes the design of a programmable QAM transceiver for VDSL applications. A 12-b DAC with 64-dB spurious-free dynamic range (SFDR) at 75-MS/s and an 11-b ADC with 72.3-dB SFDR at 70-MS/s are integrated in this complete physical layer IC. A digital IIR notch filter is included in order to not interrupt existing amateur radio bands. The proposed dual loop AGC adjusts the gain of a variable gain amplifier (VGA) to obtain maximum SNR while avoiding saturation. Using several low power techniques, the total power consumption is reduced to 300-mW at 1.8-V core and 3.3-V I/O supplies. The transceiver is fabricated in a 0.18-µm CMOS process and the chip size is 5-mm 5-mm. This VDSL transceiver supports 13-Mbps data rate over a 9000-ft channel with a BER < 10^-7.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_8_1367/_p

Copy

@ARTICLE{e87-c_8_1367,
author={Hyoungsik NAM, Tae Hun KIM, Yongchul SONG, Jae Hoon SHIM, Beomsup KIM, Yong Hoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 300-mW Programmable QAM Transceiver for VDSL Applications},
year={2004},
volume={E87-C},
number={8},
pages={1367-1375},
abstract={This paper describes the design of a programmable QAM transceiver for VDSL applications. A 12-b DAC with 64-dB spurious-free dynamic range (SFDR) at 75-MS/s and an 11-b ADC with 72.3-dB SFDR at 70-MS/s are integrated in this complete physical layer IC. A digital IIR notch filter is included in order to not interrupt existing amateur radio bands. The proposed dual loop AGC adjusts the gain of a variable gain amplifier (VGA) to obtain maximum SNR while avoiding saturation. Using several low power techniques, the total power consumption is reduced to 300-mW at 1.8-V core and 3.3-V I/O supplies. The transceiver is fabricated in a 0.18-µm CMOS process and the chip size is 5-mm 5-mm. This VDSL transceiver supports 13-Mbps data rate over a 9000-ft channel with a BER < 10^-7.},
keywords={},
doi={},
ISSN={},
month={August},}

Copy

TY - JOUR
TI - A 300-mW Programmable QAM Transceiver for VDSL Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 1367
EP - 1375
AU - Hyoungsik NAM
AU - Tae Hun KIM
AU - Yongchul SONG
AU - Jae Hoon SHIM
AU - Beomsup KIM
AU - Yong Hoon LEE
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2004
AB - This paper describes the design of a programmable QAM transceiver for VDSL applications. A 12-b DAC with 64-dB spurious-free dynamic range (SFDR) at 75-MS/s and an 11-b ADC with 72.3-dB SFDR at 70-MS/s are integrated in this complete physical layer IC. A digital IIR notch filter is included in order to not interrupt existing amateur radio bands. The proposed dual loop AGC adjusts the gain of a variable gain amplifier (VGA) to obtain maximum SNR while avoiding saturation. Using several low power techniques, the total power consumption is reduced to 300-mW at 1.8-V core and 3.3-V I/O supplies. The transceiver is fabricated in a 0.18-µm CMOS process and the chip size is 5-mm 5-mm. This VDSL transceiver supports 13-Mbps data rate over a 9000-ft channel with a BER < 10^-7.
ER -