This paper describes a technique for background digital multistage calibration in the removal of nonlinearities caused by design limitations in pipelined analog-to-digital converters (ADCs). Foreground initialization reduces the calibration time. Furthermore, an improved background skip-and-fill method enables the ADC to trace environmental changes. This method uses a least mean square adaptive algorithm that is digitally implemented with a significantly reduced number of tap coefficients.

In this paper, an indoor repeater antenna with high isolation for WCDMA application is proposed. The designed repeater has very small separation of 20 mm between the donor and server antennas. The antenna has two resonance frequencies to cover the WCDMA band from 1.92 GHz to 2.17 GHz. The fabricated antenna has VSWR below 1.5, gain over 8 dBi, and isolation between server and donor antennas less than -80 dB in the WCDMA band.

An internal antenna with a system ground for digital video broadcasting-handheld (DVB-H) service is proposed. The proposed antenna consists of a main patch with a two-step slit, two additional elements, and a system ground. The antenna has a small volume, 36 mm 11 mm 6 mm, and an average gain of -2.22 dBi to -0.06 dBi over the DVB-H band.

In this paper, a compact and wideband printed monopole antenna is proposed. The proposed antenna is fed by CPW line and has two stubs for impedance matching. A simple monopole element has resonance frequency of 2.5 GHz (low resonance frequency). High resonance frequency of 5.5 GHz and wideband characteristic can be achieved by adjusting the position and size of stubs. The designed antenna has dimension of 0.125 λ0 height and 0.16 λ0 width where λ0 is the free-space wavelength at 2.5 GHz. The measured bandwidth of the antenna is 3.56 GHz (2.47-6.03 GHz) for S11 less than -10 dB. FDTD method is used to analyze the proposed antenna with wideband characteristic.

This letter describes an efficient architecture for a Software Defined Radio (SDR) Wideband Code Division Multiple Access (WCDMA) receiver using for high performance wireless communication systems. The architecture is composed of a Radio Frequency (RF) front-end, an Analog-to-Digital Converter (ADC), and a Quadrature Amplitude Modulation (QAM) demodulator. A coherent demodulator, with a complete digital synchronization scheme, achieves the bit-error rate (BER) of 10-6 with the implementation loss of 0.5 dB for a raw Quadrature Phase Shift King (QPSK) signal.