IEICE TRANSACTIONS on Fundamentals
Optimal Loop Bandwidth Design for Low Noise PLL Applications
Summary :
This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications, Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.
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- IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.10 pp.1979-1985
- Publication Date
- 1997/10/25
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- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Kyoohyun LIM, Seung Hee CHOI, Beomsup KIM, "Optimal Loop Bandwidth Design for Low Noise PLL Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 10, pp. 1979-1985, October 1997, doi: .
Abstract: This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications, Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_10_1979/_p
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@ARTICLE{e80-a_10_1979,
author={Kyoohyun LIM, Seung Hee CHOI, Beomsup KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Optimal Loop Bandwidth Design for Low Noise PLL Applications},
year={1997},
volume={E80-A},
number={10},
pages={1979-1985},
abstract={This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications, Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Optimal Loop Bandwidth Design for Low Noise PLL Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1979
EP - 1985
AU - Kyoohyun LIM
AU - Seung Hee CHOI
AU - Beomsup KIM
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1997
AB - This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications, Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.
ER -
English
