Realizing frequency rectangular characteristics using a planar circuit made of a normal conductor material such as a printed circuit board (PCB) is difficult. The reason is that the corners of the frequency response are rounded by the effect of the low unloaded quality factors of the resonators. Rectangular frequency characteristics are generally realized by a low-noise amplifier (LNA) with flat gain characteristics and a high-order bandpass filter (BPF) with resonators having high unloaded quality factors. Here, we use an LNA and a fourth-order flat passband BPF made of a PCB to realize the desired characteristics. We first calculate the signal and noise powers to confirm any effects from insertion loss caused by the BPF. Next, we explain the design and fabrication of an LNA, since no proper LNAs have been developed for this research. Finally, the rectangular frequency characteristics are shown by a circuit combining the fabricated LNA and the fabricated flat passband BPF. We show that rectangular frequency characteristics can be realized using a flat passband BPF technique.

Matching circuits using LC elements are widely applied to high-frequency circuits such as power amplifier (PA) and low-noise amplifier (LNA). For determining matching condition of multi-stage matching circuits, this paper shows that any multi-stage LC-Ladder matching circuit with resistive termination can be decomposed to the extended L-type matching circuits with resistive termination containing negative elements where the analytical solution exists. The matching conditions of each extended L-type matching circuit are obtained easily from the termination resistances and the design frequency. By synthesizing these simple analysis solutions, it is possible to systematically determine the solution even in a large number of stages (high order) matching circuits.

This paper presents on-wafer noise figure (NF) de-embedding method of differential low noise amplifier (LNA). The characterization of NF was set up and referred as multi-stage network. The Friis law was applied to improve from the noise contributions from the subsequent stages. The correlated differential NF is accurately obtained after de-embedding the noise contribution from the interconnections and external components. Details of equations and measurement procedure are reported in this work. A 2.4GHz differential LNA was tested to demonstrate the feasibility of measurement and showed precise NF compared with other methods. The result shows an NF of 0.57dB achieved using de-embedding method and 1.06dB obtained without the de-embedding method. This is an improvement of 0.49dB of NF measurement.

We report on robust and low-power-consumption InP- and GaN-HEMT Low-Noise-Amplifiers (LNAs) operating in Q-band frequency range. A multi-stage common-gate (CG) amplifier with current reuse topology was used. To improve the survivability of the CG amplifier, we introduced a feedback resistor at the gate bias feed. The design technique was adapted to InP- and GaN-HEMT LNAs. The 75nm gate length InP HEMT LNA exhibited a gain of 18dB and a noise figure (NF) of 3dB from 33 to 50GHz. The DC power consumption was 16mW. The Robustness of the InP HEMT LNA was tested by injecting a millimeter-wave input power of 13dBm for 10 minutes. No degradation in a small signal gain was observed. The fabricated 0.12µm gate length GaN HEMT LNA exhibited a gain of 15dB and an NF of 3.2dB from 35 to 42GHz. The DC power consumption was 280mW. The LNA survived until an input power of 28dBm.

This paper addresses a noise matching problem for MIMO receiver with mutual coupling in the presence of signal and antenna noise coupling. The matching network in this paper is designed to maximize the system's ergodic capacity by means of minimizing the noise figure matrix. For reducing RF circuit complexity, low noise matching design without crossover elements of the matching circuit is derived for compact symmetrical 2$ imes$2 MIMO receiver system with mutually coupled antenna. Numerical simulation verifies our analytical results and demonstrates the superiority of the proposed matching method among feasible ones. The paper furthermore investigates the lossy matching circuit with the corresponding circuit parameters in a specific condition and the effect of practical matching circuit.

Single front-end architecture with parasitic antenna element (PAE) in compact array system has been proposed for enhancing spectral efficiency and miniaturizing the receiver. Although most of studies paid attention to design optimal receiver with antenna mutual coupling on fading correlation, relatively little attention has been paid to noise. In this paper, we propose a low noise model for single front-end MIMO receiver system with PAE which includes arbitrary signal and noise coupling. The proposed model articulates physical noise sources and relates their spatial correlation with array receive antennas, parasitic element, front-end and matching circuit. A matching circuit is designed to achieve minimum noise figure. After that, the optimal PAE value is derived to maximize channel capacity. We present numerical analysis to verify the proposed system on certain conditions.

A 315 MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40 nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11 µW power consumption at 315 MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4 µW with 7.9 dB noise figure and 20.5 dB gain in state-of-the-art designs.

At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (Dgd) has been enlarged to obtain a better maximum available gain (MAG). By using the asymmetric-layout transistor, a 0.6 dB MAG improvement is realized when Dgd changes from 60 nm to 200 nm. A four-stage common-source low noise amplifier is implemented in a 65 nm CMOS process. A measured peak power gain of 24 dB is achieved with a power dissipation of 30 mW from a 1.2-V power supply. An 18 dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17 GHz from 51 GHz to 68 GHz, and noise figure (NF) is from 4.0 dB to 7.6 dB.

An inductorless low noise amplifier (LNA) with active balun for digital TV (DTV) applications is presented. The LNA exploits a noise cancellation technique which allows for simultaneous wide-band impedance matching and low noise design. The matching and amplifier stages in the LNA topology perform single-ended to differential signal conversion with balanced output. The second and third-order nonlinearity of the individual amplifiers as well as the distortion caused by the interaction between the stages are suppressed to achieve high IIP2 and IIP3. A method for intrinsic cancellation of the second-order interaction is employed to reduce the dependence of the IIP3 on the frequency spacing between the interfering signals in the two-tone test of DTV tuners. Fabricated in a 0.18 µm CMOS technology, the LNA core size is 0.21 mm2. Measurements show that the LNA IIP3 and IIP2 are +12 dBm and +21 dBm, respectively. The IIP3 variation is less than 5 dB in the 10 MHz to 200 MHz frequency spacing range. A voltage gain of 14.5 dB and a noise figure below 4 dB are achieved in a frequency range from 100 MHz to 1 GHz. The LNA consumes 11 mA from a 1.8 V supply voltage.

The noise performance of common source and cascode topology 60 GHz LNAs is analyzed and verified. The analysis result shows that the noise performance of the cascode topology is degraded at high frequency due to the inter-stage node capacitance. The analysis result is verified by experimental results. A three-stage LNA employing two noise-matched CS stages and a cascode stage is proposed. For comparison a conventional two-stage cascode LNA is also been studied with the measurement-based model. The measured results of the proposed LNA show that an input and output matching of less than -10 dB, a maximum gain of 9.7 dB and a noise figure (NF) of 3.2 dB are obtained with a power consumption of 30 mW from a 1.2-V supply voltage. Compared to the conventional cascode LNA, an improvement of 2.3-dB for NF and 1.9-dB for power gain are realized. Both the proposed and conventional LNAs are implemented in 65 nm CMOS process.

We present a highly integrated quasi-millimeter-wave receiver MMIC that integrates 22 circuits in a 3 2.3 mm area using three-dimensional MMIC (3D-MMIC) technology. The MMIC achieves low noise (3 dB) and high gain (41 dB) at 26 GHz by using an on-chip image reject filter. It integrates a multiply-by-eight (X8) local oscillator (LO) chain with the IF frequency of the 2.4 GHz band and can use low-cost voltage-controlled oscillators (VCOs) and demodulators in a 2–3 GHz frequency band. Multilayer inductors contribute to the miniaturization especially in a 2–12 GHz frequency band. Furthermore, it achieves a high dynamic range by using two step attenuators with a new built-in inverter using an N-channel depression field-effect transistor (FET). The power consumption of the MMIC is only 450 mW.

In this work, a V-band low noise amplifier (LNA) is developed in a commercial 0.13 µm RFCMOS technology. Common-source (CS) topology, known to show a better noise performance than the cascode topology, was adopted and 4-stage was employed to achieve a sufficient gain at the target frequency near the cutoff frequency fT. The measured gain was 18.6 dB with VDD = 1.2 V and increased up to 20.2 dB with VDD = 1.8 V at 66 GHz. The measured NF showed a minimum value of 7.0 dB at 62 GHz. DC power consumption was 24 mW with VDD = 1.2 V. The size of the fabricated circuit is as compact as 0.45 mm 0.69 mm. This work was further extended to investigate the effect of dummy fills on LNA performance. An identical LNA, except for the dummy fills formed very close to (and under) the metal lines of spiral inductors and interconnects, was also fabricated and compared with the standard LNA. A peak gain degradation of 3.6 dB and average NF degradation of 1.3 dB were observed, which can be ascribed to the increased mismatch and line loss due to the dummy fills.

High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.

A resistive feedback-based inductive source degeneration ultra-wideband (UWB) CMOS low noise amplifier (LNA) with floating n-well terminals has been proposed. The resistive feedback technique provides wideband input matching with a small amount of noise degradation by reducing the quality factor of the input resonant circuit. In addition, all n-wells terminals of the triple-well RF transistors are connected to the supply voltage through high value resistors in order to reduce unwanted parasitic capacitances, leading to improvement of the RF performance of the proposed LNA. The proposed UWB LNA is implemented in 0.13 µm CMOS technology and all inductors are fully integrated in this work. Measurement results show a power gain of 10 dB from 3 GHz to 6 GHz, a minimum (maximum) noise figure of 2.3 dB (3.8 dB), an input return loss of better than -8 dB, and an input referred IP3 of -7 dBm. The fabricated chip consumes only 5 mA from a 1.5 V supply voltage.

In this paper, a fully integrated 5 GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18 µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1 GHz to 6.1 GHz (relative value of 17.9%) and phase noise of lower than -110.8 dBc/Hz at 1 MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182 dBc/Hz.

Architecture of a low power Ternary Content Addressable Memory (TCAM) is proposed. The TCAM is a powerful engine for search and sort processing, but it has two serious problems, large power consumption and large power line noise. To solve these problems, we have developed a charge recycling scheme for match lines and search lines. A combination of the newly introduced PMOS CAM cell together with the conventional NMOS CAM cell realizes match line charge recycling. A checkerboard arrangement of the NMOS and the PMOS cell array enables search line charge recycling. By using these technologies, the power consumption of the TCAM can be reduced to 50% of conventional designs, and as a result, the power line noise is also reduced. An experimental chip has been fabricated in 180-nm 6-metal process. The power consumption of this chip is 6.3 fJ/bit/search, which is half of the conventional scheme.

A 0.13-µm CMOS 2.4-GHz low-noise balun-mixer is proposed, where a noise-canceling transconductance stage is adopted for low-noise characteristics. A current-bleeding circuit with an LC resonator is also adopted to further improve the noise figure of the proposed balun-mixer, without additional DC power consumption. The measured results show a DSB NF of 5.5 dB over output IF frequency ranges of 10 to 100 MHz, a conversion gain of 19 dB, and an input P1 dB of -16 dBm. The proposed balun-mixer is implemented in 0.13-µm CMOS technology and consumes only 4.5 mA from a 1.5-V supply voltage.

In this paper, we present the development of an advanced MMIC receiver for a 94-GHz band passive millimeter-wave (PMMW) imager. Our configuration is based on a Dicke receiver in order to reduce fluctuations in the detected voltage. By introducing an electronic switch in the MMIC, we achieved a high resolution millimeter-wave image in a shorter image collection time compared to that with a conventional mechanical chopper. We also developed an imaging array using MMIC receivers.

In this paper, a compact channel thermal noise model for short-channel MOSFETs is presented and applied to the radio frequency integrated circuit (RFIC) design. Based on the analysis of the relationship among different short-channel effects such as velocity saturation effect (VSE), channel-length modulation (CLM), and carrier heating effect (CHE), the compact model for the channel thermal noise was analytically derived as a simple form. In order to simulate MOSFET's noise characteristics in circuit simulators, an appropriate methodology is proposed. The used compact noise model is verified by comparing simulated results to the measured data at device and circuit level by using 65 nm and 130 nm CMOS technologies, respectively.

The GaAs industry has been growing immensely during recent years. This is mainly driven by the tremendous growth of the wireless communication market, which is still continuously growing. Additionally, an emerging mmW market with applications in automotive, defense and optoelectronics is further driving the demand for GaAs components. The two largest European GaAs fabrication companies, UMS and Filtronic are very well positioned to address the complete frequency range from 1 GHz up to 100 GHz for commercial, high volume low cost markets, as well as individual niche applications. An overview of the companies' structures, their processes and design capabilities and also their new product developments will be presented in this paper.