This work shows a broadband, high-efficiency power amplifier (PA) monolithic microwave integrated circuit (MMIC) that uses InP-based metal-oxide-semiconductor (MOS) high-electron-mobility transistors (HEMTs) with an extended drain-side access region and broadband conjugate matching topology. Advanced device technologies, namely, double-side-doped structures, MOS gate structures, and asymmetric gate recess, were adopted, and the length of the drain-side access region was optimized to simultaneously obtain high power and efficiency. A common-source PA MMIC based on InP-based MOS-HEMTs was fabricated, and an interstage circuit was designed to maximize the S21 per unit stage in the broadband, resulting in a record-high power-added efficiency and wide bandwidth.

Second harmonic signal feedback technique is applied to an HBT power amplifier for Wide-band CDMA (W-CDMA) mobile communication system to improve its linearity and efficiency. This paper describes the feedback effect of the 2nd harmonic signal from the output of the amplifier to the input on the 3rd order intermodulation distortion (IMD) products and Adjacent Channel leakage Power (ACP) of the power amplifier. The feedback amplifier, using an InGaP/GaAs HBT with 48 fingers of 3 20 µ m emitter, exhibits a 10 dB reduction in the level of the 3rd order IMD products. In addition, an ACP improvement of 7 dB for the QPSK modulation signal with a chip rate of 4.096 Mcps at 1.95 GHz was realized. As a result, the amplifier achieves a power-added efficiency of 41.5%, gain of 15.3 dB, and ACP of 43.0 dBc at a 5 MHz offset frequency and output power of 27.5 dBm. At the output power of 28 dBm, the power-added efficiency increases to 43.3% with an ACP of 40.8 dBc.

We report on robust and low-power-consumption InP- and GaN-HEMT Low-Noise-Amplifiers (LNAs) operating in Q-band frequency range. A multi-stage common-gate (CG) amplifier with current reuse topology was used. To improve the survivability of the CG amplifier, we introduced a feedback resistor at the gate bias feed. The design technique was adapted to InP- and GaN-HEMT LNAs. The 75nm gate length InP HEMT LNA exhibited a gain of 18dB and a noise figure (NF) of 3dB from 33 to 50GHz. The DC power consumption was 16mW. The Robustness of the InP HEMT LNA was tested by injecting a millimeter-wave input power of 13dBm for 10 minutes. No degradation in a small signal gain was observed. The fabricated 0.12µm gate length GaN HEMT LNA exhibited a gain of 15dB and an NF of 3.2dB from 35 to 42GHz. The DC power consumption was 280mW. The LNA survived until an input power of 28dBm.

We have developed InGaP-channel field effect transistors (FETs) with high breakdown voltages that can be fabricated by using conventional GaAs FET fabrication processes. The buffer and barrier layers were also optimized for the realization of high-voltage operation. The InGaP-channel FET has an extremely high on-state drain-to-source breakdown voltage of over 40 V, and a gate-to-drain breakdown voltage of 55 V. This enabled high-voltage large-signal operation at 40 V. The third-order intermodulation distortion of the InGaP channel FETs was 10-20 dB lower than that of an equivalent GaAs-channel FET, due to the high operating voltage.

We developed a 32-bit pseudorandom number generator (RNG) operating at liquid nitrogen temperature based on HEMT ICs. It generates maximum-length-sequence codes whose primitive polynomial is X47+X42+1 with the period of 247-1 clock cycle. We designed and fabricated three kinds of cryogenic HEMT IC for this system: A 1306-gate controller IC, a 3319-gate pseudorandom number generator (RNG) IC, and a buffer IC containing a 4-kb RAM and 514 gates. We used 0.6-µm gate-length Se-doped GaAlAs/GaAs HEMTs. Interconnects were Al for the first layer and Au/Pt/Ti for the second layer with a SiON insulator between them. The HEMT ICs have direct-coupled FET logic (DCFL) gates internally and emitter-coupled logic (ECL) compatible input-putput buffers. The unloaded basic delay of the DCFL gate was 17 ps/gate with a power consumption of 1.4 mW/gate at liquid nitrogen temperature. We used an automatic cryogenic wafer probe we developed and an IC tester for function tests, and used a high-speed performance measuring system we also developed with a bandwidth of more than 20 GHz for high-speed performance tests. Power dissipations were 3.8 W for the controller IC, 4.5 W for the RNG IC, and 3.0 W for the buffer IC. The RNG IC, the largest of the three HEMT ICs, had a maximum operating clock rate of 1.6 GHz at liquid nitrogen temperature. We submerged a specially developed zirconium ceramic printed circuit board carrying the HEMT ICs in a closed-cycle cooling system. The HEMT ICs were flip-chip-packaged on the board with bumps containing indium as the principal component. We confirmed that the RNG system operates at liquid nitrogen temperature and measured a minimum system clock period of 1.49 ns.

We developed a 300-GHz high gain amplifier MMIC in 75-nm InP high electron mobility transistor technology. We approached the issues with accurate characterization of devices to design the amplifier. The on-wafer through-reflect-line calibration technique was used to obtain accurate transistor characteristics. To increase measurement accuracy, a highly isolated structure was used for on-wafer calibration standards. The common source amplifier topology was used for achieving high gain amplification. The implemented amplifier MMIC exhibited a gain of over 25 dB in the 280-310-GHz frequency band.

This paper presents the analytical results of the effects of jitter and intersymbol interference (ISI) on a millimeter-wave impulse radio (IR) transceiver, compared with the performance of a developed 10-Gb/s W-band IR-transmitter prototype. The IR transmitter, which is compact and cost-effective, consists of a pulse generator (PG) that creates an extremely short pulse, a band-pass filter (BPF) that shapes the short pulse to the desired millimeter-wave pulse (wavelet), and an optional power amplifier. The jitters of the PG and ISI from the BPF are a hindrance in making the IR transceiver robust and in obtaining excellent performance. One analysis verified that, because of a novel retiming architecture, the random jitter and the data-dependent jitter from the PG give only a small penalty of < 0.5-dB increase in the signal-to-noise ratio (SNR) for achieving a bit error rate (BER) of < 10-12. An alternative analysis on the effect of ISI from the BPF indicated that using a Gaussian BPF enables a transmission with a BER of < 10-12 up to a data rate of 1.4 times as large as the bandwidth of the BPF, which is twice as high as that of a conventional amplitude shift keying (ASK) system. The analysis also showed that the IR system is more sensitive to the ISI than the ASK system and suggested that the mismatching of the skirt characteristics of the developed BPF with those of a Gaussian BPF causes tail lobes following the wavelet, resulting in an on/off ratio of 15 dB and hence, an SNR penalty of 6 dB.

In this paper, we describe the operation of circuits capable of more than 40-Gbit/s that we have developed using InP HEMT technology. For example, we succeeded in obtaining 43-Gbit/s operation for a full-rate 4:1Multiplier (MUX), 50-Gbit/s operation for a Demultiplexer (DEMUX), 50-Gbit/s operation for a D-type flip-flop (D-FF), and a preamplifier with a bandwidth of 40 GHz. In addition, the achievement of 90-Gbit/s operation for a 2:1MUX and a distributed amplifier with over 110-GHz bandwidth indicates that InP HEMT technology is promising for system operations of over 100 Gbit/s. To achieve these results, we also developed several design techniques to improve frequency response above 80 GHz including a symmetric and separated layout of differential elements in the basic SCFL gate and inverted microstrip.

A wide-bandwidth fundamental mixer operating at a frequency above 110GHz for precise spectrum analysis was developed using the InP HEMT technology. A single-ended resistive mixer was adopted for the mixer circuit. An IF amplifier and LO buffer amplifier were also developed and integrated into the mixer chip. As for packaging into a metal block module, a flip-chip bonding technique was introduced. Compared to face-up mounting with wire connections, flip-chip bonding exhibited good frequency flatness in signal loss. The mixer module with a built-in IF amplifier achieved a conversion gain of 5dB at an RF frequency of 135GHz and a 3-dB bandwidth of 35GHz. The mixer module with an LO buffer amplifier operated well even at an LO power of -20dBm.

We report the first monolithic integration of InGaAs/InAlAs resonant tunneling diode (RTD) and high electron mobility transistor (HEMT) epitaxially grown on an InP substrate. The transconductance for a 1-µm gate HEMT was 430 mS/mm and the peak-to-valley current ratio of the RTD was 5.1. Using the integrated structure, we demonstrate basic digital circuits to show low power characteristics of an RTD-load inverter and a static RAM cell circuit, consisting of a single transistor with two RTDs on the transistor. The memory cell circuit exhibits bistability, based on the RTD's negative differential resistance (NDR), at supply voltages from 0.6 to 1.1 V. The static power consumption was 7.3 µW/gate for the inverter and 3.0 µW for memory cell.