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Hitoshi TANAKA Masakazu AOKI Jun ETOH Masashi HORIGUCHI Kiyoo ITOH Kazuhiko KAJIGAYA Tetsurou MATSUMOTO
To improve the stability and the power supply rejection ratio (PSRR) of the voltage limiter circuit used in high-density DRAM's we present a voltage limiter circuit with pole-zero compensation. Analytical expressions that describe the stability of the circuit are provided for comprehensive consideration of circuit design. Voltage limiters with pole-zero compensation are shown to have excellent performance with respect to the stability, PSRR, and circuit area occupation. The parasitic resistances in internal voltage supply lines, signal transmission lines, and transistors are important parameters determining the stability of pole-zero compensation. Evaluation of a 16-Mbit test device revealed internal voltage fluctuations of 6% during operation of a chip-internal circuit, a phase margin of 53, and a PSRR of 30 dB.
Hirotake KAJII Masato ISE Hitoshi TANAKA Takahiro OHTOMO Yutaka OHMORI
The effects of the gate dielectrics on ambipolar transport in top-gate-type polymer light-emitting transistors with single-layer and bilayer gate dielectrics are investigated. Hole field-effect mobility is dependent on the dielectric constant of the gate dielectric onto the active layer. Hole transport of devices is affected by the dipolar disorder in the first gate dielectric layer on the active layer. Electron threshold voltage tends to decrease with increasing the total stacked gate capacitance.
Hitoshi TANAKA Yoshinobu NAKAGOME Jun ETOH Eiji YAMASAKI Masakazu AOKI Kazuyuki MIYAZAWA
A new reference voltage generator with ultralow standby current of less than 1 µA is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-µm process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm/ from room temperature to 100, and output noise of less than 12 mV for 1 Vp-p Vcc bumping are achieved. These results are sufficient for achieving high-density battery operated DRAM's with low active and data-retention currents comparable to SRAM's.
Kouji TSUNODA Akira SATO Hiroko TASHIRO Toshiro NAKANISHI Hitoshi TANAKA
A direct tunneling memory (DTM) with ultra-thin tunnel oxide and depleted floating gate has been proposed for low power embedded RAM. To achieve excellent charge retention characteristics with ultra-thin tunnel oxide, floating gate depletion is adopted to utilize the band bending at the interface between floating gate and tunnel oxide in charge retention period. The depleted floating gate is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. These effects were evaluated by the device and process simulations and confirmed by the experimental data. As a consequence, both fast programming time and superior retention time have been achieved, which is a promising performance as a low power embedded RAM for system-on-a-chip (SoC) applications.
Naoki HARA Yasuhiro NAKASHA Toshihide KIKKAWA Kazukiyo JOSHIN Yuu WATANABE Hitoshi TANAKA Masahiko TAKIKAWA
We have developed InGaP-channel field effect transistors (FETs) with high breakdown voltages that can be fabricated by using conventional GaAs FET fabrication processes. The buffer and barrier layers were also optimized for the realization of high-voltage operation. The InGaP-channel FET has an extremely high on-state drain-to-source breakdown voltage of over 40 V, and a gate-to-drain breakdown voltage of 55 V. This enabled high-voltage large-signal operation at 40 V. The third-order intermodulation distortion of the InGaP channel FETs was 10-20 dB lower than that of an equivalent GaAs-channel FET, due to the high operating voltage.