Recent discussions on increasing the efficiency of the Internet's infrastructure have centered on removing the shared Domain Name System (DNS) resolver and using a local resolver instead. In terms of the cache mechanism, this would involve removing the shared cache from the Internet. Although the removal of unnecessary parts tends to simplify the overall system, such a large configuration change would need to be analyzed before their actual removal. This paper presents our analysis on the effect of a shared DNS resolver based on campus network traffic. We found that (1) this removal can be expected to amplify the DNS traffic to the Internet by about 3.9 times, (2) the amplification ratio of the root DNS is much higher (about 6.3 times), and (3) removing all caching systems from the Internet is likely to amplify the DNS traffic by approximately 16.0 times. Thus, the removal of the shared DNS resolver is not a good idea. Our data analysis also revealed that (4) many clients without local caches generate queries repeatedly at short intervals and (5) deploying local caches is an attractive technique for easing DNS overhead because the amount of traffic from such clients is not small.

The back-propagation algorithm has been applied to many fields, and has shown large capability of neural networks. Many people use the back-propagation algorithm together with a momentum term to accelerate its convergence. However, in spite of the importance for theoretical studies, theoretical background of a momentum term has been unknown so far. First, this paper explains clearly the theoretical origin of a momentum term in the back-propagation algorithm for both a batch mode learning and a pattern-by-pattern learning. We will prove that the back-propagation algorithm having a momentum term can be derived through the following two assumptions: 1) The cost function is Enαn-µEµ, where Eµ is the summation of squared error at the output layer at the µth learning time and a is the momentum coefficient. 2) The latest weights are assumed in calculating the cost function En. Next, we derive a simple relationship between momentum, learning rate, and learning speed and then further discussion is made with computer simulation.

We study the coupled spatio-temporal variations of the electron density and the electric field (electron plasma oscillations) in high-electron mobility transistors using the developed device model. The excitation of electron plasma oscillations in the terahertz range of frequencies might lead to the emission of terahertz radiation. In the framework of the model developed, we calculate the resonant plasma frequencies and find the conditions for the plasma oscillations self-excitation (plasma instability) We show that the transit-time effect in the high-electric field region near the drain edge of the channel of high-electron mobility transistors can cause the self-excitation of the plasma oscillations. It is shown that the self-excitation of plasma oscillations is possible when the ratio of the electron velocity in the high field region, ud, and the gate length, Lg, i.e., the inverse transit time are sufficiently large in comparison with the electron collision frequency in the gated channel, ν. The transit-time mechanism of plasma instability under consideration can superimpose on the Dyakonov-Shur mechanism predicted previously strongly affecting the conditions of the instability and, hence, terahertz emission. The instability mechanism under consideration might shed light on the origin of terahertz emission from high electron mobility transistors observed in recent experiments.

A direct tunneling memory (DTM) with ultra-thin tunnel oxide and depleted floating gate has been proposed for low power embedded RAM. To achieve excellent charge retention characteristics with ultra-thin tunnel oxide, floating gate depletion is adopted to utilize the band bending at the interface between floating gate and tunnel oxide in charge retention period. The depleted floating gate is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. These effects were evaluated by the device and process simulations and confirmed by the experimental data. As a consequence, both fast programming time and superior retention time have been achieved, which is a promising performance as a low power embedded RAM for system-on-a-chip (SoC) applications.

A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less than 1-µm spacing between the n and pMOSFETs is achieved by using a retrograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-µm n-gate load pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-µm p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etching using a plasma-TEOS silicone-dioxide mask. The newly developed memory cell was demonstrated using 0.25-µm CMOS process technology. A 6.93-µm2 and 1-V operation full CMOS SRAM cell with a high-performance circuit was achieved by a simple fabrication process.