Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications
Summary :
A direct tunneling memory (DTM) with ultra-thin tunnel oxide and depleted floating gate has been proposed for low power embedded RAM. To achieve excellent charge retention characteristics with ultra-thin tunnel oxide, floating gate depletion is adopted to utilize the band bending at the interface between floating gate and tunnel oxide in charge retention period. The depleted floating gate is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. These effects were evaluated by the device and process simulations and confirmed by the experimental data. As a consequence, both fast programming time and superior retention time have been achieved, which is a promising performance as a low power embedded RAM for system-on-a-chip (SoC) applications.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.608-613
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.608
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
- Category
- Memory
Authors
Keyword
Latest Issue
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Kouji TSUNODA, Akira SATO, Hiroko TASHIRO, Toshiro NAKANISHI, Hitoshi TANAKA, "Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 608-613, April 2005, doi: 10.1093/ietele/e88-c.4.608.
Abstract: A direct tunneling memory (DTM) with ultra-thin tunnel oxide and depleted floating gate has been proposed for low power embedded RAM. To achieve excellent charge retention characteristics with ultra-thin tunnel oxide, floating gate depletion is adopted to utilize the band bending at the interface between floating gate and tunnel oxide in charge retention period. The depleted floating gate is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. These effects were evaluated by the device and process simulations and confirmed by the experimental data. As a consequence, both fast programming time and superior retention time have been achieved, which is a promising performance as a low power embedded RAM for system-on-a-chip (SoC) applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.608/_p
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@ARTICLE{e88-c_4_608,
author={Kouji TSUNODA, Akira SATO, Hiroko TASHIRO, Toshiro NAKANISHI, Hitoshi TANAKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications},
year={2005},
volume={E88-C},
number={4},
pages={608-613},
abstract={A direct tunneling memory (DTM) with ultra-thin tunnel oxide and depleted floating gate has been proposed for low power embedded RAM. To achieve excellent charge retention characteristics with ultra-thin tunnel oxide, floating gate depletion is adopted to utilize the band bending at the interface between floating gate and tunnel oxide in charge retention period. The depleted floating gate is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. These effects were evaluated by the device and process simulations and confirmed by the experimental data. As a consequence, both fast programming time and superior retention time have been achieved, which is a promising performance as a low power embedded RAM for system-on-a-chip (SoC) applications.},
keywords={},
doi={10.1093/ietele/e88-c.4.608},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 608
EP - 613
AU - Kouji TSUNODA
AU - Akira SATO
AU - Hiroko TASHIRO
AU - Toshiro NAKANISHI
AU - Hitoshi TANAKA
PY - 2005
DO - 10.1093/ietele/e88-c.4.608
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - A direct tunneling memory (DTM) with ultra-thin tunnel oxide and depleted floating gate has been proposed for low power embedded RAM. To achieve excellent charge retention characteristics with ultra-thin tunnel oxide, floating gate depletion is adopted to utilize the band bending at the interface between floating gate and tunnel oxide in charge retention period. The depleted floating gate is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. These effects were evaluated by the device and process simulations and confirmed by the experimental data. As a consequence, both fast programming time and superior retention time have been achieved, which is a promising performance as a low power embedded RAM for system-on-a-chip (SoC) applications.
ER -
English
