In this paper, low-power design techniques of high-speed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A systematic approach to the power optimization of pipeline and parallel pipeline ADC's is introduced based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC. Finally, the theoretical minimum of required power as functions of the sampling rate, resolution and SNR is discussed. The analysis shows that, with the developments of new circuits and systems to approach to the minimum, the power can be further reduced by a factor of more than 1/10 without changing the basic architectures.

A cyclic A/D conversion circuit technique for sensor networks has been developed using 0.2-µm CMOS/FD-SOI technology. The FD-SOI analog switches can lower the supply voltage without degrading accuracy because of their negligible body effect. The proposed A/D converter achieves operation at the supply voltage of 1 V or less and can handle a sampling frequency ranging from 8 Sps to 8 kSps with a new clocking technique.

This paper describes a sub-1-V power-supply, which is useful for self-powered short-range wireless systems with ambient energy sources. A variable-stage DC-DC converter, which consists of multi-stage switched capacitor circuits and has intermittent operation with an external capacitor, makes it possible to extend the time for self-powered operation. We fabricated a variable-stage DC-DC converter and an intermittent operation circuit with a 0.8-µm CMOS/SOI process. We also applied the sub-1-V power-supply system to a self-powered short-range wireless system and verified its effectiveness.

A frequency drift of open-loop PLL is an issue for the direct-modulation applications such as Bluetooth transceiver. The drift mainly comes from a temperature variation of VCO during the transmission operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through the whole-chip thermal analysis. Moreover, a novel temperature-compensated VCO, employing a new biasing scheme, is proposed. The combination of these two techniques enables the power reduction of the transmitter by 33% without sacrificing the performance.

A GPS radio design for a complete single chip GPS receiver using 0.18-µm CMOS is presented. The complete single chip GPS receiver satisfies several key requirements for mobile applications, such as compactness, low power, and high sensitivity. The radio part, including the RF front end, the RF/IF PLLs, and IF functions, occupies 2.0 2.3 mm in a total chip area of 6.3 6.3 mm. It is fabricated using 0.18-µm CMOS technology utilizing MIM capacitors. The radio part operates within a 1.6 to 2.0 V supply voltage range and consumes 27 mW at 1.8 V. The whole GPS SoC consumes 57 mW for a fully functional chip and provides a high sensitivity of -152 dBm. The radio design features countermeasures against substrate coupling noise from the digital part.

An ultra low power CMOS SAW oscillator in the 300-MHz-band that operates on a sub-1 V supply voltage and at sub-1 mW power consumption has been developed. The SAW oscillator is fabricated in a 0.35-µm fully depleted SOI (FD-SOI) process with low voltage operation capability. The SAW oscillator is configured as a type of Colpitts oscillator but consists of 3 cascaded amplifiers instead of a single amplifier. Although the circuit configuration is quite similar to the conventional Colpitts oscillator, this proposed configuration generates an excessively high negative resistance that even exceeds the theoretical limit of the conventional one.

In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and design automation techniques to accomplish this goal. The first part of the article provides an overview of basic physics and process scaling trends that have resulted in a significant increase in the leakage currents in CMOS circuits. This part also distinguishes between the standby and active components of the leakage current. The second part of the article describes a number of circuit optimization techniques for controlling the standby leakage current, including power gating and body bias control. The third part of the article presents techniques for active leakage control, including use of multiple-threshold cells, long channel devices, input vector design, transistor stacking to switching noise, and sizing with simultaneous threshold and supply voltage assignment.

In this paper, a Dynamic Voltage and Frequency Management (DVFM) scheme introduced in a microprocessor for handheld devices with wideband embedded DRAM is reported. Our DVFM scheme reduces the power consumption effectively by cooperation of the autonomous clock frequency control and the adaptive supply voltage control. The clock frequency is controlled using hardware activity information to determine the minimum value required by the current processor load. This clock frequency control is realized without special power management software. The supply voltage is controlled according to the delay information provided from a delay synthesizer circuit, which consists of three programmable delay components, gate delay, RC delay and a rise/fall delay. The delay synthesizer circuit emulates the critical-path delay within 4% voltage accuracy over the full range of process deviation and voltage. This accurate tracking ability realizes the supply voltage scaling according to the fluctuation of the LSI's characteristic caused by the temperature and process deviation. The DVFM contributes not only the dynamic power reduction, but also the leakage power reduction. This microprocessor, fabricated in 0.18 µm CMOS embedded DRAM technology achieves 82% power reduction in a Personal Information Management scheduler (PIM) application and 40% power reduction in a MPEG4 movie playback application. As process technology shrinks, the DVFM scheme with leakage power compensation effect will become more important realizing in high-performance and low-power mobile consumer applications.

We have developed an application processor optimized for 3G cellular phones. It provides high energy efficiency by using various low power techniques. For low active power consumption, we use a hierarchical clock gating technique with a static clock gating controlled by software and a two-level dynamic clock gating controlled by hardware. This technique reduces clock power consumption by 35%. And we also apply a pointer-based pipeline to in the CPU core, which reduces the pipeline latch power by 25%. This processor contains 256 kB of on-chip user RAM (URAM) to reduce the external memory access power. The URAM read buffer (URB) enables high-throughput, low latency access to the URAM while keeping the CPU clock frequency high because the URAM read data is transferred to the URB in 256-bit widths at half the frequency of the CPU. The average miss penalty is 3.5 cycles at the CPU clock frequency, hit rate is 89% and the energy used for URAM reads is 8% less that what it would be for URAM without a URB. These techniques reduce the power consumption of the CPU core, and achieve 4500 MIPS/W at 1.0 V power supply (Dhrystone 2.1). For the low leakage requirements, we use internal power switches, and provides resume-standby (R-standby) and ultra-standby (U-standby) modes. Signals across a power boundary are transmitted through µI/O circuits to prevent invalid signal transmission. In the R-standby mode, the power supply to almost all the CPU core area, except for the URAM is cut off and the URAM is set to a retention mode. In the U-standby mode, the power supply to the URAM is also turned off for less leakage current. The leakage currents in the R-standby and in the U-standby modes are respectively only 98 and 12 µA. For quick recovery from the R-standby mode, the boot address register (BAR) and control register contents needed immediately after wake-up are saved by hardware into backup latches. The other contents are saved by software into URAM. It takes 2.8 ms to fully recover from R-standby.

A novel cache-based packet-processing-engine (PPE) architecture that achieves low-power consumption and high packet-processing throughput by exploiting the nature of network traffic is proposed. This architecture consists of a processing-unit array and a bit-stream manipulation path called a burst stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC). Network packets, which have the same information in their header, appear repeatedly over a short time. By exploiting that nature, the PLC memorizes the packet-processing method with all results (i. e. , table lookups), and applies it to other packets. The PLC enables most packets to skip the execution at the processing-unit array, which consumes high power. As a practical implementation of the cache-based PPE architecture, P-Gear was designed. In particular, P-Gear was compared with a conventional PPE in terms of silicon die size and power consumption. According to this comparison, in the case of current 0.13-µm CMOS process technology, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.8% of the power consumption required by the conventional PPE. Configurations of both architectures for the 1- to 100-Gbps throughput range were also analyzed. In the throughput range of 10-Gbps or more, P-Gear can achieve the target throughput in a smaller die size than the conventional PPE. And for the whole throughput range, P-Gear can achieve a target throughput at lower power than the conventional PPE.

Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation.

We propose a low-power resource-shared VLIW processor (RSVP) for future leaky nanometer process technologies. It consists of several single-way independent processor units (IPUs) that share parallel processor resources. Each IPU works as a variable-way VLIW processor sharing the parallel resources according to priorities of given tasks. RSVP allocates shared parallel resources to the IPUs cycle by cycle. It can minimize the number of NOPs that is wasting power. The performance per power (P³) of a 4-parallel 4-way RSVP that corresponds to four 4way VLIWs is 3.7% better than a conventional 4-parallel 4-way VLIW multiprocessor in the current 90 nm process. We estimate that the RSVP achieves 36% less leakage power and 28% better P³ in the future 25 nm process. We have fabricated an RSVP test chip that contains two IPU and a shared resource equivalent to two 2way VLIWs in a 180 nm process. It is functional at 100 MHz clock speed and its power is 130 mW.

This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ring-connected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45-73% in comparison to cases with conventional architectures for motion estimation.

Parallel execution of the carry propagate adder (CPA) and leading non-zero (LNZ) detector that processes the CPA result is a common way to reduce the latencies of floating-point instructions. However, the conventional methods usually cause one-bit errors. We developed an exact LNZ detection circuit operating in parallel with the CPA. The circuit is implemented in the floating-point unit of our newly developed embedded processor core. Circuit simulation results show that the LNZ circuit has a similar speed to the CPA, and it contributes to make a small low-power FPU for an embedded processor core.

High-speed, area-efficient, and low-power Montgomery modular multipliers for RSA algorithm have been developed for digital signature and user authentication in high-speed network systems and smart card LSIs. The multiplier-accumulators (MAC) in the developed Montgomery modular multipliers have a non-identical multiplicand/multiplier word length organization. This organization can eliminate the bandwidth bottleneck associated with a data memory, and enables to use a single-port memory for area and power reductions. The developed MAC is faster than the conventional identical word length organization due to the shortened critical path. For smart card applications, an area-efficient architecture with 42 kgates can produce 1.2 digital signatures in a second for 2,048-bit key length with the power consumption of 6.8 mW.

This paper describes a speed-oriented ultralow-voltage and low-power SOI circuit technique based on a differential enhancement- and depletion-mode (ED)-MOS circuit. Combining an ED-MOS circuit block for critical paths and a multi-V_th CMOS circuit block for noncritical paths, that is, the so-called differential ED-CMOS/SOI circuit, makes it possible to achieve low-power and ultrahigh-speed operation of over 1 GHz at a supply voltage of less than 0.5 V. As two applications of the differential ED-CMOS/SOI circuit, a multi-stage frequency divider that uses the ED-MOS circuit in a first-stage frequency divider and a pipelined adder with a CMOS pipeline register are described in detail. To verify the effectiveness of the ED-CMOS/SOI circuit scheme, we fabricated a 1/8 frequency divider and a 32-bit binary look-ahead carry (BLC) adder using the 0.25-µm MTCMOS/SOI process. The frequency divider operates down to 0.3 V with a maximum operating frequency of 3.6 GHz while suppressing power dissipation to 0.3 mW. The 32-bit adder operates at a frequency of 1 GHz at 0.5 V.

Dynamic power supply noise measurements with resolutions of 100 ps and 100 µV for 100 ns and 1 V ranges are performed at various operating frequencies up to 400 MHz on multiple points in a low power register file and SRAM for product chips by using on-chip noise detectors. The measurements show that the noises are clearly emphasized in frequency domains by the interaction of circuit operations and bias network's AC transfers. A proposed design methodology that covers a fast SPICE simulator and parasitic extractors can predict dynamic noises from power supplies, ground, well, and substrate interactions to provide robustness to the design of low power body bias control circuitry.

Several IP cells are available in the market to implement 8051-compliant microcontroller in embedded systems. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper aims at lowering the power consumption of an 8051 IP core while keeping unaltered performances, through Register Transfer Level techniques such as clustered clock gating, operand isolation and state encoding. This approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. A total power reduction of about 40% is achieved, with limited area overhead.

A radio frequency identification tag LSI operating with the carrier frequency of 13.56 MHz as well as storing nonvolatile information in embedded ferroelectric random access memory (FeRAM) has been developed. A full wave rectifier composed of PMOS transistor diodes and NMOS transistor switches achieves RF-to-DC power conversion efficiency over 54%. The entire 16 kbits write and read transaction time can be reduced to 2.1 sec by the use of FeRAM, which corresponds to 2.2 times speed enhancement over conventional EEPROM based tag LSIs. The communication range of the FeRAM based tag LSI can be effectively improved by storing antitheft information in a ferroelectric nonvolatile flip-flop, which can reduce the power consumption of FeRAM from 27 µW to 5 µW. The communication range for the antitheft gate system becomes 70 cm.

A direct tunneling memory (DTM) with ultra-thin tunnel oxide and depleted floating gate has been proposed for low power embedded RAM. To achieve excellent charge retention characteristics with ultra-thin tunnel oxide, floating gate depletion is adopted to utilize the band bending at the interface between floating gate and tunnel oxide in charge retention period. The depleted floating gate is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. These effects were evaluated by the device and process simulations and confirmed by the experimental data. As a consequence, both fast programming time and superior retention time have been achieved, which is a promising performance as a low power embedded RAM for system-on-a-chip (SoC) applications.

To realize a high-density on-chip memory, the authors have proposed a novel logic-process-compatible memory cell. This cell consists of two logic transistors, and placing a planar MIM (metal insulator metal) capacitor on a copper wire above the transistors produces a memory area of 26 F², which is approximately 60% smaller than a 6T SRAM cell. A suitable cell-bias design and a dual precharge scheme solve the coupling problem inherent in the cell and allow standard logic transistors to be used. This cell--applying the proposed schemes--can handle 10-ns cycle time at a bit-line voltage of 0.7 V. The random cycle is about three times faster than that of a conventional V_BL precharge scheme. These results indicate that the umbrella cell is a strong candidate for providing a high-density memory for SOC applications.

This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 µm² in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.

This paper describes the access-timing control for an embedded SRAM core which operates in low and wide supply voltage (V_dd = 0.3-1.5 V). In the conventional SRAMs, a wiring-replica with replica-memory-cell (RMC) to trace the delay of memory core is used for this purpose. Introducing a wiring-replica control provides the better tracing capability in the wide range of V_dd above 0.5 V than those of using the control with logic-gate-delay. However, as V_dd is reduced below 0.5 V and gets close to the threshold voltage (V_th) of transistors, the access-timing fluctuation resulting from the variation in memory-cell-transistor-drain current (I_d) is intolerably increased. As a result, the conventional control is no longer effective in such a low-voltage operation because the RMC can not replicate the variation in transistor-drain current (I_d) and V_th of the memory-cells (MCs). Thus, to trace the access-timing fluctuation caused by the variation in I_d and V_th is the prerequisite for the SRAM control in the range of V_dd = 0.3-1.5 V. To solve this issue, we have proposed new access-control scheme as follows; 1) a write-replica circuit with an asymmetrical memory cell (WRAM) making it possible to replicate the variation in I_d and V_th for the write-access timing control, and 2) a source-level-adjusted direct-sense-amplifier (SLAD) to accelerate the read-access-timing even in low V_dd. These circuit techniques were implemented in a 32-Kbit SRAM in four-metal 130-nm CMOS process technology, and have been verified a low-voltage operation of 0.3 V which has not ever reported with 6.8 MHz. Moreover it operated in wide-voltage up to 1.5 V with 960 MHz. The required 27 MHz operation for mobile applications has been demonstrated at 0.4 V which is 6-times faster than the previous reports. The WRAM scheme enabled the write operation even at 0.3 V. And the access time which can be restricted by the slow tail bits of MCs has been accelerated by 73% to 140 nsec at 0.3 V by using SLAD scheme.

We investigated the use of AlO_x:N/SiN_y stacked gate dielectric as an alternate gate dielectric, which were prepared by alternately repeating sub-nanometer deposition of Al₂O₃ from an alkylamine-stabilized AlH₃ + N₂O gas mixture and rapid thermal nitridation in NH₃. The negative fix charges, being characteristics of almina, were as many as 3.910¹² cm^-2 in the effective net charge density. The effective dielectric constant and the breakdown field were 8.9 and 8 MV/cm, respectively, being almost the same as pure Al₂O₃. And we have demonstrated that the leakage current through the AlO_x:N/SiN_y stacked gate dielectric with a capacitance equivalent thickness (CET) of 1.9 nm is about two orders of magnitude less than that of thermally-grown SiO₂. Also, we have confirmed the dielectric degradation similar to the stress-induced leakage current (SILC) mode and subsequent soft breakdown (SBD) reported in ultrathin SiO₂ under constant current stress and a good dielectric reliability comparable to thermally-grown ultrahin SiO₂. From the analysis of n⁺poly-Si gate metal-insulator-semiconductor field effect transistor (MISFET) performance, remote coulomb scattering due to changes in the gate dielectric plays an important role on the mobility degradation of MISFET with AlON/SiON gate stack.

We have fabricated poly-Si/Si_0.7Ge_0.3/Si stacked gate on 4 nm-thick SiO₂/Si(100), and examined the diffusion of Ge and impurities as a function of annealing temperature in the range of 800-1000 by energy dispersive X-ray spectroscopy (EDX) and secondary ion mass spectrometry (SIMS). It is reviealed that germanium atoms diffuse into 100 nm-thick silicon cap layer uniformly after 1000 annealing for 30 min and the crystallinity of As⁺ doped poly-SiGe is better than that of doped poly-SiGe. Also, in comparison with poly-Si gate MOS capacitors, we have confirmed that MOS capcitors with p⁺ and n⁺ SiGe gates show a 0.2 V reduction in the flat-band voltage for p⁺ gate and no change for n⁺ gate, with no increase in gate leakage current with respect to the oxide voltage. This result is attributable to the difference in the energy band structure between Si and Si_0.7Ge_0.3.

A novel NiSi technology with bi-layer Co/TiN structure as a capping layer is proposed for the highly thermal immune Ni Silicide technology. Much better thermal immunity of Ni Silicide was certified up to 700, 30 min post silicidation furnace annealing by introducing Co/TiN bi-layer capping. The proposed structure is successfully applied to nano-scale CMOSFET with a gate length of 80 nm. The sheet resistance of nano-scale gate poly shows little degradation even after the high temperature furnace annealing of 650, 30 min. The Ni/Co/TiN structure is very promising for the nano-scale MOSFET technology which needs the ultra shallow junction and high temperature post silicidation processes

We have developed separation by bonding Si islands (SBSI) process for advanced CMOS LSI applications. In this process, the Si islands that become the SOI regions are formed by selective etching of the SiGe layer in the Si/SiGe stacked layers, and those are bonded to the Si substrate with the thermal oxide layers by furnace annealing. The etching selectivity for SiGe/Si and surface roughness after the SiGe etching were found to be improved by decreasing the HNO₃ concentration in the etching solution. The thicknesses of the fabricated Si island and the buried oxide layer also became uniform by decreasing the HNO₃ concentration. In addition, it was found that the space formed by SiGe etching in the Si/SiGe stacked layers was able to be filled with the thermal oxide layer without furnace annealing.

The role of electric field in metal-induced lateral crystallization (MILC) of amorphous Si (a-Si) under limited Ni-supply condition has been investigated. The nominal lateral-growth rate was increased from 3.6 µm/h (no-electric field) to 23 µm/h at the positive electrode side and reduced to 2.8 µm/h at the negative electrode side in presence of the electric field of 20 V/cm. However, spontaneously nucleated needle-like Si crystals were observed in the enhanced positive electrode side, which have been found to be independent of the MILC. Further investigation under the condition where Ni in the supply region was removed on the way of crystallization revealed that the electric field enhanced crystallization greatly reduced. These results indicate that the electric field does not enhance the MILC growth but enhances the diffusion of Ni in a-Si which takes place prior to the MILC growth.

Poly-Si TFT (Thin Film transistor) fabricated below 170 using excimer laser crystallization of sputtered Si films was characterized. In particular, a gate insulator with a breakdown field exceeding 8 MV/cm was deposited by using ICP (Inductively Coupled Plasma) CVD (Chemical Vapor Deposition). A buffer layer possessing high thermal conductivity was inserted between the active channel and the plastic substrate, in order to protect the plastic substrate from the thermal energy of the laser and to increase adhesion of Si film on plastic. Using this method, we successfully fabricate TFT with a stable electron field-effect mobility value greater than 14.7 cm²/Vsec.

The linear operation of a HBT with a GaAs/InGaP composite collector structure is demonstrated. The composite collector structure allows for a thin collector design that is suitable for the linear operation of a HBT without critical degradation of the breakdown voltage. The load pull measurements under a 1.95 GHz WCDMA signal have shown that a composite-collector HBT with a 400-nm thick collector layer operates with power-added-efficiency (PAE) as high as 53% at V_CE = 3.5 V as a result of improved distortion characteristics. Despite the thin collector design, collector-emitter breakdown voltage of 11 V was achieved even at current density of 10 kA/cm². The composite-collector HBT has even greater advantage for future low voltage (< 3 V) applications where maintaining PAE and linearity becomes one of the critical issues.

A fully integrated voltage controlled oscillator (VCO) MMIC for millimeter-wave applications has been designed and implemented in InGaP/GaAs heterojunction bipolar transistor (HBT) technology. To achieve a fully integrated VCO, a base-emitter diode is employed as the tuning varactor, and microstrip lines are employed for the transmission lines. The fabricated VCO MMIC chip size is 0.86 mm 1.34 mm and delivers an output power of 5.1 dBm at 28.7 GHz and a free-running phase noise of -118 dBc/Hz at 1 MHz offset. The dc current consumption is only 20 mA.

We analyzed passivation film and the AlGaN surface states using open-gated structures of AlGaN/GaN HFETs by numerical simulation and experiments. From the analyses, we confirmed that insulating film conductivity plays the prominent roles in device performances of the wide bandgap semiconductor device. Device simulation confirmed that the difference in I_D-V_G characteristics is due to the trapping type of the surface states; electron-trap type or hole-trap type. For electron-trap type surface states, the surface potential pinned at electron quasi-Fermi level, which is the same as the channel potential in the open-gated FETs. As a result, surface potential of ungated region is equal to the channel electric potential resulting in the uncontrollability of the channel current by the edge placed gate electrode. For hole-trap type surface states, the surface potential is pinned at hole quasi-Fermi level, which must be the same as the edge placed gate electrode potential. Then, the AlGaN surface potential varies with the electrode potential variation allowing the control of channel current as if the whole channel is covered with a metal electrode. Experiments for open-gated FET with unpassivated surface show no current variation. This corresponds to electron-trap type surface states from the simulation. On the other hand, SiO_X evaporated open-gated FET show current control by the gate electrode. The I_D-V_G characteristics resembles in simulated I_D-V_G characteristics with hole-trap surface states. However, the estimated time constants for the trap reactions are incredibly long due to the deep energy level for the surface states in wide bandgap semiconductors. In addition, the open-gated FET showed reverse threshold shift to the value expected from the hole-trap pinning levels. So, we concluded that the no current variation for the unpassivated open-gated FET can be attributed to electron traps in the surface states, but the control of the drain current for SiO_X deposited open-gated FET is not by surface hole-traps, but by slightly conductive passivation film of SiO_X.

We propose a novel Schottky barrier diode with a dual Schottky structure combined with an AlGaN/GaN heterostructure. The purpose of this diode was to lower the on-state voltage and to maintain the high reverse breakdown voltage. An AlGaN/GaN heterostructure was grown using a metalorganic chemical vapor deposition (MOCVD). The Schottky barrier diode with a dual Schottky structure was fabricated on the AlGaN/GaN heterostructure. As a result, the on-voltage of the diode was below 0.1 V and the reverse breakdown voltage was over 350 V.

A new high ruggedness Power MOSFET structure with a planar oxide self align p⁺ implant structure is proposed and discussed. We compare the proposed self-align process with the conventional p⁺ MASK process and contact p⁺ implant process. It is shown that the self align implant structure with a wide p⁺ area can reduce the parasitic BJT effect and, therefore, improve the device's avalanche energy capability, which is required for inductive load circuits. Based on the unclamped inductive load switching measurement results, the proposed device avalanche energy with self align p⁺ implant process is improved about 355% as compared to the traditional one.

Based on the similarity in current-voltage characteristics of resonant-tunneling diodes (RTDs) and tunneling-type superconductive Josephson junctions, novel current-mode logic circuits consisting of four RTDs have been proposed. NAND and NOR functions, as well as AND and OR, can be obtained in a simple circuit configuration. SPICE simulation showed that the present circuits can operate at a clock frequency as high as 200 GHz.

Hydrogenated germanium films were fabricated in the thickness range of 7-98 nm on SiO₂ at 150 by an rf glow discharge decomposition of 0.25% GeH₄ diluted with H₂, and the nucleation and growth of Ge nanocrystallites were measured from topographic and current images simultaneously taken by a conductive AFM probe after Cr contact formation on films so prepared. We have demonstrated that current images show fine grains in comparison with topographic images and the lateral evolution of the Ge grains with progressive film growth. The contrast in current images can be interpreted in terms of the difference in electron concentration between nanocrystalline grains and their boundaries.

We have fabricated Al-gate MOS capacitors with a Si quantum-dots (Si-QDs) floating gate, the number of dots was changed in the range of 1.6-4.810¹¹ cm^-2 in areal density with repeating the formation of Si dots and their surface oxidation a couple of times. The capacitance-voltage (C-V) characteristics of Si-QDs floating gate MOS capacitors on p-Si(100) confirm that, with increasing number of dots density, the flat-band voltage shift due to electron charging in Si-QDs is increased and the accumulation capacitance is decreased. Also, in the negative bias region beyond the flat-band condition, the voltage shift in the C-V curves due to the emission of valence electrons from intrinsic Si-QDs was observed with no hysterisis presumably because holes generated in Si-QDs can smoothly recombine with electrons tunneling through the 2.8 nm-thick bottom SiO₂. In addition, we have demonstrated the charge retention characteristic improves in the Si-QDs stacked structure.

This paper deals with a TE plane wave reflection and transmission from a one-dimensional random slab by means of the stochastic functional approach. The relative permittivity of the random slab is written by a Gaussian random field in the vertical direction with finite thickness, and is uniform in the horizontal direction with infinite extent. An explicit form of the random wavefield is obtained in terms of a Wiener-Hermite expansion with approximate expansion coefficients (Wiener kernels) under a small fluctuation case. By using the first three terms of the random wavefield representation, the optical theorem is illustrated in figures for several physical parameters. It is then found that the optical theorem holds with good accuracy.

In this paper, amplified double Rayleigh backscattering noise (DRB) in the optical fiber Raman amplifier is analyzed. Expressions are present for both forward pumping and backward pumping schemes, respectively. Calculation is performed to show the effective suppression of DRB noise by employing an optical isolator. The best isolator position is determined as 13 km away from the signal input end for forward pumping, and 9 km from the output end for backward pumping. The best position is found insensitive to the fiber length, pump power, and signal power. When the isolator is on the best position, the DRB noise can be reduced by almost 2 to 3 orders.

A novel bias circuit providing a stable quiescent current for temperature and supply voltage variations is proposed and implemented to a W-CDMA MMIC power amplifier. The power amplifier with the proposed bias circuit has the quiescent current variation of only 6% for the -30 to 90 temperature change, and 8.5% for the 2.9 V to 3.1 V supply voltage change, and the variation of the power gain at the 28 dBm output power is less than 0.8 (0.05) dB for the 0.1 V of supply voltage (60 of temperature) variation.

For the power amplifier used in CDMA cellular phones, the supply voltage is switched between high and low at a transmission power several decibels higher than 10 dBm using a DC-DC converter to improve operational efficiency. The longer the operation time under low supply voltage, the lower the current consumption of the cellular phone. In order to increase the output power under low supply voltage, we applied the 2nd harmonic-injection technique, which is useful for distortion compensation. With 2nd harmonic-injection, there is an inflectional power point. The distortion increases rapidly when output power goes beyond the inflectional power point. It is important to make this inflectional power point high in order to compensate for distortion in the high output-power region. We report here that the inflectional power point can be increased by connecting a 2nd harmonic short circuit to the drain terminal of the FET to which the 2nd harmonic for distortion compensation is injected. A prototype of the final stage of the power amplifier under a supply voltage of V_dd=1.5 V is presented. We report that applying a CDMA uplink signal, 1.5 dB higher output power and 12% higher drain efficiency is achieved compared when only 2nd harmonic injection is employed.

A new hybrid method for characterizing the irregular power/ground plane pair is developed in this paper by combining the conventional eigen-mode expansion method with the new-presented inverted composition method and a simple model order reduction. By the approach, the eigen-mode expansion method can be extended to the characteristics research of the power/ground plane pair with holes. In this gridless method, ports and decoupling capacitors can be arbitrarily placed on the plane pair. The numerical example demonstrates its good validity.

This paper presents two new intelligent methods to linearize the Multi-Carrier Power Amplifiers (MCPA). One of the them is based on the Neuro-Fuzzy controller while the other uses two small neural networks as a polar predistorter. Neuro-Fuzzy controllers are not model based, and hence, have ability to control the nonlinear systems with undetermined parameters. Both methods are adaptive, low complex, and can be implemented in base-band part of the communication systems. The performance of the linearizers is obtained via simulation. The simulation is performed for three different scenarios; namely, a multi-carrier amplifier for GSM with four channels, a CDMA amplifier and a multi-carrier amplifier with two tones. The simulation results show that Neuro-Fuzzy Controller (NFC) and Neural Network Polar Predistorter (NNPP) have higher efficiencies so that reduce IMD3 by more than 42 and 32 dB, respectively. The practical implementation aspects of these methods are also discussed in this paper.

High performance delay-locked loop (DLL) is key to the high data rate chip-to-chip communication, suggesting the output jitter, due to power noise, bang-bang noise, temperature-voltage drift, etc, should be properly controlled. In this paper, high speed DRAM operation can be achieved by a dual loop DLL with various novel techniques; a new counting code with hysteretic bit-transitions can remove the large DAC glitches by preventing the binary bit-transitions in the locking states. A delay buffer, which is insensitive to the power supply fluctuations, is proposed. The voltage-temperature (VT) dependencies of the feedback path and the open clock path are balanced, minimizing the VT shift of the clock. As a result, the high-speed DRAM interface with the maximized setup/hold window can be accomplished.

A new Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) scheme is proposed to suppress leakage current by two orders of magnitude in the SRAM's for sub-70 nm process technology with sub-1-V V_DD. This two-order leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. In addition, metal shields are proposed to be inserted between the cell nodes and the bit lines not to allow the cell nodes to be flipped by the external bit-line coupling noise in this paper. A test chip has been fabricated to verify the effectiveness of the RRDSV scheme with the metal shields by using 0.18-µm CMOS process. The retention voltages of SRAM's with the metal shields are measured to be improved by as much as 40-60 mV without losing the stored data compared to the SRAM's without the shields.

This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filters for temperature- and power supply- insensitive voltage references. The proposed RC low-pass filters reduce reference settling time at heavy R&C loads and improve switching noise performance without conventional off-chip bypass capacitors. The prototype ADC fabricated in a 0.25 µm CMOS occupies the active die area of 2.25 mm² and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.

An all-digital CMOS duty cycle correction (DCC) circuit with a fixed rising edge was proposed to achieve the wide correction ranges of input duty cycle and PVT variations, the low standby power and the fast recovery from the standby mode for use in multi-phase clock systems. SPICE simulations showed that this DCC adjusts the output duty cycle to 500.7% for the wide range of input duty cycle from 15% to 85% at the input frequency of 1 GHz, within the commercial range of PVT corners. The all-digital implementation and the use of a toggle flip flop at the input stage enabled the wide correction ranges of PVT variations and input duty cycle, respectively.