Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits

Farzan FALLAH; Massoud PEDRAM

doi:10.1093/ietele/e88-c.4.509

Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits

Farzan FALLAH, Massoud PEDRAM

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In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and design automation techniques to accomplish this goal. The first part of the article provides an overview of basic physics and process scaling trends that have resulted in a significant increase in the leakage currents in CMOS circuits. This part also distinguishes between the standby and active components of the leakage current. The second part of the article describes a number of circuit optimization techniques for controlling the standby leakage current, including power gating and body bias control. The third part of the article presents techniques for active leakage control, including use of multiple-threshold cells, long channel devices, input vector design, transistor stacking to switching noise, and sizing with simultaneous threshold and supply voltage assignment.

Publication: IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.509-519

Publication Date: 2005/04/01

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DOI: 10.1093/ietele/e88-c.4.509

Type of Manuscript: Special Section INVITED PAPER (Special Section on Low-Power LSI and Low-Power IP)

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Farzan FALLAH, Massoud PEDRAM, "Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits" in IEICE TRANSACTIONS on Electronics, vol. E88-C, no. 4, pp. 509-519, April 2005, doi: 10.1093/ietele/e88-c.4.509.
Abstract: In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and design automation techniques to accomplish this goal. The first part of the article provides an overview of basic physics and process scaling trends that have resulted in a significant increase in the leakage currents in CMOS circuits. This part also distinguishes between the standby and active components of the leakage current. The second part of the article describes a number of circuit optimization techniques for controlling the standby leakage current, including power gating and body bias control. The third part of the article presents techniques for active leakage control, including use of multiple-threshold cells, long channel devices, input vector design, transistor stacking to switching noise, and sizing with simultaneous threshold and supply voltage assignment.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.509/_p

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@ARTICLE{e88-c_4_509,
author={Farzan FALLAH, Massoud PEDRAM, },
journal={IEICE TRANSACTIONS on Electronics},
title={Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits},
year={2005},
volume={E88-C},
number={4},
pages={509-519},
abstract={In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and design automation techniques to accomplish this goal. The first part of the article provides an overview of basic physics and process scaling trends that have resulted in a significant increase in the leakage currents in CMOS circuits. This part also distinguishes between the standby and active components of the leakage current. The second part of the article describes a number of circuit optimization techniques for controlling the standby leakage current, including power gating and body bias control. The third part of the article presents techniques for active leakage control, including use of multiple-threshold cells, long channel devices, input vector design, transistor stacking to switching noise, and sizing with simultaneous threshold and supply voltage assignment.},
keywords={},
doi={10.1093/ietele/e88-c.4.509},
ISSN={},
month={April},}

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TY - JOUR
TI - Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 509
EP - 519
AU - Farzan FALLAH
AU - Massoud PEDRAM
PY - 2005
DO - 10.1093/ietele/e88-c.4.509
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and design automation techniques to accomplish this goal. The first part of the article provides an overview of basic physics and process scaling trends that have resulted in a significant increase in the leakage currents in CMOS circuits. This part also distinguishes between the standby and active components of the leakage current. The second part of the article describes a number of circuit optimization techniques for controlling the standby leakage current, including power gating and body bias control. The third part of the article presents techniques for active leakage control, including use of multiple-threshold cells, long channel devices, input vector design, transistor stacking to switching noise, and sizing with simultaneous threshold and supply voltage assignment.
ER -